View ZL5002206_736906.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL50022 Enhanced 4 K Digital Switch with Stratum 4E DPLL
Data Sheet Features
* 4096 channel x 4096 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps 32 serial TDM input, 32 serial TDM output streams Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 4E specifications Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output) DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs
ZL50022GAC ZL50022QCC ZL50022QCG1 ZL50022GAG2 Ordering Information 256 Ball PBGA 256 Lead LQFP 256 Lead LQFP* 256 Ball PBGA**
November 2006
* *
*Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40C to +85C
Trays Trays Trays Bake & Drypack Trays, Bake & Drypack
* * *
* *
Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Output streams can be configured as bidirectional for connection to backplanes Per-stream input and output data rate conversion selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Input and output data rates can differ
VSS RESET ODE
VDD_CORE
VDD_IO
VDD_COREA
VDD_IOA
STi[31:0] FPi CKi MODE_4M0 MODE_4M1 REF0 REF1 REF2 REF3 REF_FAIL0 REF_FAIL1 REF_FAIL2 REF_FAIL3
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ Control
STOHZ[15:0]
DPLL
Output Timing
FPo[3:0] CKo[5:0] FPo_OFF[2:0]
OSC_EN
OSC
Internal Registers & Microprocessor Interface
Test Port
TDi
OSCo
DS_RD
R/W_WR
Figure 1 - ZL50022 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
D[15:0]
A[13:0]
OSCi
TRST
TMS
TCK
TDo
IRQ
CS
ZL50022
* * * * * * * * * * * * * * * * * Per-stream high impedance control outputs (STOHZ) for 16 output streams Per-stream input bit delay with flexible sampling point selection Per-stream output bit and fractional bit advancement Per-channel ITU-T G.711 PCM A-Law/-Law Translation Four frame pulse and six reference clock outputs Three programmable delayed frame pulse outputs Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses: 61 ns, 122 ns, 244 ns
Data Sheet
Per-channel constant or variable throughput delay for frame integrity and low latency applications Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151 Per-channel high impedance output control Per-channel message mode Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Applications
* * * * * * * PBX and IP-PBX Small and medium digital switching platforms Remote access servers and concentrators Wireless base stations and controllers Multi service access platforms Digital Loop Carriers Computer Telephony Integration
2
Zarlink Semiconductor Inc.
ZL50022
Description
Data Sheet
The ZL50022 is a maximum 4,096 x 4,096 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50022 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudo-random bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32-bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter attenuation. The jitter attenuation function exceeds the Stratum 4E specification. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
3
Zarlink Semiconductor Inc.
ZL50022 Table of Contents
Data Sheet
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 External High Impedance Control, STOHZ0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.0 Device Operation in Master Mode and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 Master Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2 Divided Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.3 Multiplied Slave Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.0 Overall Operation of the DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 DPLL Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.3 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.3.1 Automatic Reference Switching Without Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1.3.2 Automatic Reference Switching With Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.1.4 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.1.5 DPLL Internal Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.0 DPLL Frequency Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.1 Input Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.2 Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.3 Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.4 Pull-In/Hold-In Range (also called Locking Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.0 Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.1 Input Clock Cycle to Cycle Timing Variation Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4
Zarlink Semiconductor Inc.
ZL50022 Table of Contents
Data Sheet
15.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.3 Phase Alignment Speed (Phase Slope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.4 Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.5 Single Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.6 Multiple Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 18.0 Pseudo-random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 19.0 PCM A-law/m-law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20.0 Quadrant Frame Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 21.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 21.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 21.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 22.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 23.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 24.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 24.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 25.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 27.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5
Zarlink Semiconductor Inc.
ZL50022 List of Figures
Data Sheet
Figure 1 - ZL50022 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50022 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . 11 Figure 3 - ZL50022 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0="11" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11 - Output Timing for CKo4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 14 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 15 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 18 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 19 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 20 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 21 - Automatic Reference Switching State Diagram with No Preferred Reference . . . . . . . . . . . . . . . . . . 40 Figure 22 - Automatic Reference Switching State Diagrams with Preferred Reference . . . . . . . . . . . . . . . . . . . . 42 Figure 23 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 24 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 25 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 26 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 30 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 33 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 34 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 35 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 37 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . 104 Figure 38 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . 105 Figure 39 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 40 - Output Drive Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 41 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 47 - CKo5 Timing Diagram (19.44 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 48 - REF0 - 3 Reference Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6
Zarlink Semiconductor Inc.
ZL50022 List of Figures
Data Sheet
Figure 49 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7
Zarlink Semiconductor Inc.
ZL50022 List of Tables
Data Sheet
Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 2 - CKi and FPi Configurations for Multiplied Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 7 - ZL50022 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8 - Preferred Reference Selection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 9 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 10 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 11 - Values for Single Period Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 12 - Multi-period Hysteresis Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 13 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 14 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 15 - Quadrant Frame Bit Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 16 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 18 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 19 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 23 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 25 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 27 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 28 - DPLL Control Register (DPLLCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 29 - Reference Frequency Register (RFR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 30 - Centre Frequency Register - Lower 16 Bits (CFRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 31 - Centre Frequency Register - Upper 10 Bits (CFRU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 32 - Frequency Offset Register (FOR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 33 - Lock Detector Threshold Register (LDTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 34 - Lock Detector Interval Register (LDIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 35 - Slew Rate Limit Register (SRLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 36 - Reference Change Control Register (RCCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 37 - Reference Change Status Register (RCSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38 - Interrupt Register (IR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39 - Interrupt Mask Register (IMR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 40 - Interrupt Clear Register (ICR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 41 - Reference Failure Status Register (RSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 42 - Reference Mask Register (RMR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 43 - Reference Frequency Status Register (RFSR) Bits - Read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 44 - Output Jitter Control Register (OJCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 45 - Stream Input Control Register 0 - 31 (SICR0 - 31) BIts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 47 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8
Zarlink Semiconductor Inc.
ZL50022 List of Tables
Data Sheet
Table 49 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 50 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 52 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 55 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9
Zarlink Semiconductor Inc.
ZL50022
Changes Summary
The following table captures the changes from January 2006 to November 2006. Page 1 Item Change Updated Ordering Information.
Data Sheet
The following table captures the changes from the October 2004 issue. Page 39, 70, 71 Item Section12.1, "DPLL Timing Modes" on page 39 RCCR Register bits "FDM1 - 0" on page 70 RCSR Register bits "DPM1 - 0" on page 71 * Change The on-chip DPLL's normal, holdover, automatic, and freerun modes are now collectively referred to as DPLL timing modes instead of operation modes. This change is to avoid confusion with the two main device operating modes; the master and slave modes. Section 12.1.3.1 and Section 12.1.3.2 added to clarify the DPLL's automatic reference switching with and without preference operations in Automatic Timing Mode. Clarified threshold calculations. Added description to clarify that only two consecutive references can be used in automatic timing mode with a preferred reference.
40
Section12.1.3.1, "Automatic Reference Switching Without Preferences" on page 40 and Section12.1.3.2, "Automatic Reference Switching With Preferences" on page 41 Table 33, Lock Detector Threshold Register (LDTR) Bits Table 36, "Reference Change Control Register (RCCR) Bits" Bits "PRS1 - 0" and Bits "PMS2 - 0"
*
67 69
* *
10
Zarlink Semiconductor Inc.
ZL50022
1.0
1.1
1
A
Data Sheet
Pinout Diagrams
BGA Pinout
2 STi29 STi10 STi9 STi11 STi14 STi15 RESET VSS VDD_IOA VSS VDD_ COREA NC NC NC NC STio28 2 3 STi28 STi5 VSS VDD_IO STi8 STi12 IC_GND VSS VDD_IOA TMS TRST TDi VDD_IO VSS STOHZ0 STio29 3 4 STi27 STi4 STi7 STi3 VDD_IO STi13 IC_ OPEN VDD_ COREA VSS VSS TCK D0 STio0 STio1 STio2 STio31 4 5 STi25 CKo2 STi6 STi2 VSS VDD_IO TDo CKo5 VSS VDD_ COREA VDD_IO VSS STOHZ3 STio3 STOHZ2 STio30 5 6 STi26 STi0 STi1 CKo4 VDD_ CORE VDD_ CORE VDD_IO VSS CKo3 VDD_IO VDD_ CORE VDD_ CORE D1 STOHZ1 D2 NC 6 7 STi24 CKo0 CKo1 REF3 REF_ FAIL3 VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D5 D3 D4 NC 7 8 NC REF2 REF_ FAIL2 REF1 REF_ FAIL1 VSS VSS VSS VSS VSS VSS D6 D7 D8 D9 NC 8 9 NC VDD_ COREA VSS REF_ FAIL0 REF0 VSS VSS VSS VSS VSS VSS D10 D11 D14 D12 NC 9 10 STio22 FPi IC_ OPEN VSS NC VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D13 IRQ D15 NC 10 11 STio23 CKi IC_ OPEN FPo_ OFF1 VDD_ CORE VDD_ CORE VDD_IO A7 A3 VDD_IO VDD_ CORE VDD_ CORE R/W _WR STio5 CS NC 11 12 STio21 IC_ OPEN OSCo OSC_ EN VSS VDD_IO A12 A9 A4 IC_ OPEN VDD_IO VSS DTA_ RDY 13 STio20 IC_ OPEN IC_GND STio13 VDD_IO IC_ OPEN A13 A10 A5 A0 STio10 MOT _INTEL STio4 14 NC OSCi VSS VDD_IO STio12 FPo3 FPo1 FPo_ OFF0 A8 A2 STio11 MODE_ 4M0 VDD_IO VSS STio6 NC 14 15 NC ODE STio15 STio14 FPo2 FPo_ OFF2 FPo0 A11 A6 A1 STio9 STio8 STOHZ5 STOHZ7 STio7 NC 15 16 VSS STio19 STio18 STio16 STio17
A
VSS STi31
B
B
C STi30
C
D STi17
D
E
STi16 STi19
E
F
STOHZ15 F STOHZ14 G STOHZ12 H STOHZ13 J STOHZ11 K STOHZ10 L STOHZ9 M STOHZ8 NC NC VSS 16
N
G STi18
H STi21
J
STi20 STi22 STi23
K
L
M STio25
N STio24
P STio26 R STio27
STOHZ4 STOHZ6 DS_RD NC 12 MODE_ 4M1 NC 13
P
R
T
VSS 1
T
Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50022 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
11
Zarlink Semiconductor Inc.
ZL50022
1.2 QFP Pinout
Data Sheet
STi28 STi29 VDD_IO STi30 STi31 STi_8 VSS STi_9 STi_10 STi_11 STi_12 STi_13 STi_14 STi_15 VDD_IO IC_GND VSS IC_OPEN RESET TDo VDD_CORE VSS NC VSS VDD_COREA VSS NC VDD_IOA CKo5 VSS VSS VDD_COREA NC VDD_IOA CKo3 VSS NC VSS VDD_COREA VSS VDD_CORE TMS VSS NC NC TCK TRST TDi VDD_IO VSS STi_16 STi_17 STi_18 STi_19 STi_20 STi_21 VDD_IO STi_22 VSS STi_23 STio_24 STio_25 STio_26
194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
STi27 STi26 STi25 STi24 VSS STi_7 VDD_IO STi_6 STi_5 STi_4 STi_3 STi_2 STi_1 STi_0 VSS VDD_IO CKo4 VSS CKo2 VDD_CORE CKo1 VSS CKo0 VDD_IO REF3 REF_FAIL3 REF2 REF_FAIL2 REF1 REF_FAIL1 VSS REF0 VDD_IO REF_FAIL0 VSS VDD_COREA VSS FPi CKi IC_OPEN IC_OPEN IC_OPEN IC_OPEN OSCo OSCi VSS VDD_CORE VSS IC_GND VDD_IO VSS ODE NC NC NC NC NC NC NC VDD_IO STio_23 STio_22 STio_21 STio_20
STio_27
STio_19 STio_18 STio_17 STio_16 STOHZ_15 VSS STOHZ_14 VDD_IO STOHZ_13 STOHZ_12 STio_15 STio_14 STio_13 STio_12 VSS VDD_IO FPo3 VSS FPo2 VDD_CORE FPo_OFF2 OSC_EN FPo1 IC_OPEN FPo_OFF1 VSS FPo0 VDD_IO FPo_OFF0 A13 A12 VSS A11 VDD_CORE A10 A9 A8 A7 A6 A5 A4 A3 A2 VSS A1 VDD_CORE A0 VSS IC_OPEN VDD_IO STOHZ_11 STOHZ_10 STOHZ_9 STOHZ_8 STio_11 STio_10 STio_9 VSS STio_8 VDD_IO NC NC NC NC
VSS D13 D14 D15 R/W_WR CS MOT_INTEL DS_RD IRQ DTA_RDY VDD_CORE MODE_4M0 VSS MODE_4M1 VDD_IO VSS STio_4 STio_5 STio_6 STio_7 STOHZ_4 STOHZ_5
STio_28 STio_29 STio_30 STio_31 VDD_IO STio_0 STio_1 VSS STio_2 STio_3 STOHZ_0 STOHZ_1 STOHZ_2 STOHZ_3 VDD_IO D0 VSS D1 VDD_CORE D2 VSS D3 D4 D5 D6 D7 D8 D9 VDD_IO D10 VSS D11 VDD_CORE
Figure 3 - ZL50022 256-Lead 28 mm x 28 mm LQFP (top view)
12
Zarlink Semiconductor Inc.
STOHZ_6
STOHZ_7
VDD_IO
VSS NC NC NC NC
D12
ZL50022
2.0 Pin Description
LQFP Pin Number 19, 33, 45, 83, 95, 109, 146, 173, 213, 233 217, 231, 157, 224 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 241, 249 220, 226 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251 Pin Name VDD_CORE Description Power Supply for the core logic: +1.8 V
Data Sheet
PBGA Pin Number E6, E11, F6, F7, F10, F11, L6, L7, L10, L11, M6, M7, M10, M11 H4, K5, B9, L2 D3, D14, E4, E13, F5, F12, G6, G11, K6, K11, L5, L12, N3, N14
VDD_COREA VDD_IO
Power Supply for analog circuitry: +1.8V Power Supply for I/O: +3.3 V
J2, J3 A1, A16, C3, C9, C14, D10, E5, E12, F8, F9, G7, G8, G9, G10, H2, H3, H6, H7, H8, H9, H10, J4, J5, J7, J8, J9, J10, K2, K4, K7, K8, K9, K10, L8, L9, M5, M12, P3, P14, T1, T16
VDD_IOA VSS
Power Supply for the CKo5 and CKo3 outputs: +3.3V Ground
13
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number K3 LQFP Pin Number 234 Pin Name TMS Description
Data Sheet
Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic. Test Reset (5 V-Tolerant Input with Internal Pull-up) Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. When JTAG is not being used, this pin should be pulled low during normal operation. Test Serial Data In (5 V-Tolerant Input with Internal Pull-up) JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Serial Data Out (5 V-Tolerant Three-state Output) JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected.
L4
238
TCK
L3
239
TRST
M3
240
TDi
G5
212
TDo
B12, B13, C10, C11, F13, G4, K12 C13, G3 A8, A9, A14, A15, E10, M2, N2, P2, P16, R2, R16, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15
80, 105, 150, 151, 152, 153, 210 144, 208 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 215, 219, 225, 229, 236, 237
IC_OPEN
IC_GND NC
Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low. No Connect These pins MUST be left unconnected.
14
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number M14, R13 LQFP Pin Number 46, 48 Pin Name MODE_4M0, MODE_4M1 Description
Data Sheet
4M Input Clock Mode 0 to 1 (5V-Tolerant Input with internal pull-down) These two pins should be tied together and are typically used to select CKi = 4.096MHz operation. See Table 7, "ZL50022 Operating Modes" on page 38 for a detailed explanation. See Table 17, "Control Register (CR) Bits" on page 53 for CKi and FPi selection using the CKIN1 - 0 bits. Oscillator Enable (5 V-Tolerant Input with Internal Pull-down) If tied high, this pin indicates that there is a 20 MHz external oscillator interfacing with the device. If tied low, there is no oscillator and CKi will be used for master clock generation. If the device is in master mode, an external oscillator is required and this pin MUST be tied high. Oscillator Clock Output (3.3 V Output) If OSC_EN = `1', this pin should be connected to a 20 MHz crystal (See Figure 23 on page 90) or left unconnected if a clock oscillator is connected to OSCi pin under normal operation (See Figure 24 on page 91). If OSC_EN = 0, this pin MUST be left unconnected. Oscillator Clock Input (3.3 V Input) If OSC_EN = `1', this pin should be connected to a 20 MHz crystal (See Figure 23 on page 90) or to a clock oscillator under normal operation (See Figure 24 on page 91). If OSC_EN = 0, this pin MUST be driven high or low by connecting either to VDD_IO or to ground. DPLL Reference Inputs 0 to 3 (5 V-Tolerant Schmitt-Triggered Inputs) If the device is in Master mode, these input pins accept 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz timing references independently. One of these inputs is defined as the preferred or forced input reference for the DPLL. The Reference Change Control Register (RCCR) selects the control of the preferred reference.These pins are ignored if the device is in slave mode unless SLV_DPLLEN (bit 13) in the Control Register (CR) is set. When these input pins are not in use, they MUST be driven high or low by connecting either to VDD_IO or to ground. Failure Indication for DPLL References 0 to 3 (5 V-Tolerant Three-state Outputs) These output pins are used to indicate input reference failure when the device is in master mode. If REF0 fails, REF_FAIL0 will be driven high. If REF1 fails, REF_FAIL1 will be driven high. If REF2 fails, REF_FAIL2 will be driven high. If REF3 fails, REF_FAIL3 will be driven high. If the device is in slave mode, these pins are driven low, unless SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
D12
107
OSC_EN
C12
149
OSCo
B14
148
OSCi
E9, D8, B8, D7
161, 164, 166, 168
REF0 - 3
D9, E8, C8, E7
159, 163, 165, 167
REF_FAIL0 - 3
15
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number G15, G14, E15, F14 LQFP Pin Number 102, 106, 110, 112 Pin Name FPo0 - 3 Description
Data Sheet
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant Three-state Outputs) FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output clock of CKo0. FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output clock of CKo1. FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output clock of CKo2. FPo3: Programmable 8 kHz frame pulse corresponding to 4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock of CKo3. In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot be narrower than the input frame pulse (FPi) width. Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant Three-state Outputs) Individually programmable 8 kHz frame pulses, offset from the output frame boundary by a programmable number of channels. Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame Pulse Output (5 V-Tolerant Three-state Output) As FPo_OFF2, this is an individually programmable 8 kHz frame pulse, offset from the output frame boundary by a programmable number of channels. By programming the FP19EN (bit 10) of FPOFF2 register to high, this signal becomes FPo5, a non-offset frame pulse corresponding to the 19.44 MHz clock presented on CKo5. FPo5 is only available in Master mode or when the SLV_DPLLEN bit in the Control Register is set high while the device is in one of the slave modes. ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant Three-state Outputs) CKo0: 4.096 MHz output clock. CKo1: 8.192 MHz output clock. CKo2: 16.384 MHz output clock. CKo3: 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz programmable output clock. CKo4: 1.544 MHz or 2.048 MHz programmable output clock. CKo5: 19.44 MHz output clock See Section 6.0 on page 24 for details. In Divided Slave mode, the frequency of CKo0 - 3 cannot be higher than input clock (CKi). CKo4 and CKo5 are only available in Master mode or when the SLV_DPLLEN bit in the Control Register is set high while the device is in one of the slave modes.
H14, D11
100, 104
FPo_OFF0 - 1
F15
108
FPo_OFF2 or FPo5
B7, C7, B5, J6, D6, H5
170, 172, 174, 227, 176, 221
CKo0 - 5
16
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number B10 LQFP Pin Number 155 Pin Name FPi Description
Data Sheet
ST-BUS/GCI-Bus Frame Pulse Input (5 V-Tolerant Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. The frame pulse frequency is 8 kHz. The frame pulse associated with the highest input or output data rate must be applied to this pin when the device is operating in Divided Slave mode or Master mode. The exception is if the device is operating in Master mode with loopback (i.e., CKi_LP is set in the Control Register). In that case, this input must be tied high or low externally. When the device is operating in Multiplied Slave mode, the frame pulse associated with the highest input data rate must be applied to this pin. For all modes (except Master mode with loopback), if the data rate is 16.384 Mbps, a 61 ns wide frame pulse must be used. By default, the device accepts a negative frame pulse in ST-BUS format, but it can accept a positive frame pulse instead if the FPINP bit is set high in the Control Register (CR). It can accept a GCI-formatted frame pulse by programming the FPINPOS bit in the Control Register (CR) to high. ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered The Input) This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock. The clock frequency associated with twice the highest input or output data rate must be applied to this pin when the device is operating in either Divided Slave mode or Master mode. The exception is if the device is operating in Master mode with loopback (i.e., CKi_LP is set in the Control Register). In that case, this input must be tied high or low externally. The clock frequency associated with twice the highest input data rate must be applied to this pin when the device is operating in Multiplied Slave mode. In all modes of operation (except Master mode with loopback), when data is running at 16.384 Mbps, a 16.384 MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR).
B11
154
CKi
17
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number B6, C6, D5, D4, B4, B3, C5, C4, E3, C2, B2, D2, F3, F4, E2, F2, E1, D1, G1, F1, J1, H1, K1, L1, A7, A5, A6, A4, A3, A2, C1, B1 LQFP Pin Number 179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4 11, 12, 13, 14, 55, 56, 58, 59, 75, 76, 77, 78, 119, 120, 122, 124 Pin Name STi0 - 31 Description
Data Sheet
Serial Input Streams 0 to 31 (5 V-Tolerant Inputs with Enabled Internal Pull-downs) The data rate of each input stream can be selected independently using the Stream Input Control Registers (SICR[n]). In the 2.048 Mbps mode, these pins accept serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins accept serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins accept serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins accept TDM data streams at 16.384 Mbps with 256 channels per frame.
N4, P4, R4, P5, N13, P11, R14, R15, M15, L15, L13, L14, E14, D13, D15, C15, D16, E16, C16, B16, A13, A12, A10, A11, N1, M1, P1, R1, T2, T3, T5, T4 R3, P6, R5, N5, P12, N15, P13, P15, N16, M16, L16, K16, H16, J16, G16, F16
STio0 - 31
Serial Output Streams 0 to 31 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os with Enabled Internal Pull-downs) The data rate of each output stream can be selected independently using the Stream Output Control Registers (SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins output serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins output serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins output serial TDM data streams at 16.384 Mbps with 256 channels per frame. These output streams can be used as bi-directionals by programming BDH (bit 7) and BDL (bit 6) of Internal Mode Selection (IMS) register.
STOHZ0 - 15
Serial Output Streams High Impedance Control 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state Outputs) These pins are used to enable (or disable) external three-state buffers. When an output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel. When the STio channel is active, the STOHZ drives low for the duration of the corresponding output channel. STOHZ outputs are available for STio0 - 15 only.
18
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number B15 LQFP Pin Number 141 Pin Name ODE Description
Data Sheet
Output Drive Enable (5 V-Tolerant Input with Internal Pull-up) This is the output enable control for STio0 - 31 and the output-driven-high control for STOHZ0 - 15. When it is high, STio0 - 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are tristated and STOHZ0 - 15 are driven high. Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os) These pins form the 16-bit data bus of the microprocessor port.
M4, N6, R6, P7, R7, N7, M8, N8, P8, R8, M9, N9, R9, N10, P9, R10
16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38 44
D0 - 15
N12
DTA_RDY
Data Transfer Acknowledgment_Ready (5 V-Tolerant Three-state Output) This active low output indicates that a data bus transfer is complete for the Motorola interface. For the Intel interface, it indicates a transfer is completed when this pin goes from low to high. An external pull-up resistor MUST hold this pin at HIGH level for the Motorola mode. An external pull-down resistor MUST hold this pin at LOW level for the Intel mode. Chip Select (5 V-Tolerant Input) Active low input used by the Motorola or Intel microprocessor to enable the microprocessor port access. Read/Write_Write (5 V-Tolerant Input) This input controls the direction of the data bus lines (D0 - 15) during a microprocessor access. For the Motorola interface, this pin is set high and low for the read and write access respectively. For the Intel interface, a write access is indicated when this pin goes low. Data Strobe_Read (5 V-Tolerant Input) This active low input works in conjunction with CS to enable the microprocessor port read and write operations for the Motorola interface. A read access is indicated when it goes low for the Intel interface. Address 0 to 13 (5 V-Tolerant Inputs) These pins form the 14-bit address bus to the internal memories and registers.
R11
40
CS
N11
39
R/W_WR
R12
42
DS_RD
K13, K15, K14, J11, J12, J13, J15, H11, J14, H12, H13, H15, G12, G13
82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99
A0 - 13
19
Zarlink Semiconductor Inc.
ZL50022
PBGA Pin Number M13 LQFP Pin Number 41 Pin Name MOT_INTEL Description
Data Sheet
Motorola_Intel (5 V-Tolerant Input with Enabled Internal Pull-up) This pin selects the Motorola or Intel microprocessor interface to be connected to the device. When this pin is unconnected or connected to high, Motorola interface is assumed. When this pin is connected to ground, Intel interface should be used. Interrupt (5 V-Tolerant Three-state Output) This programmable active low output indicates that the internal operating status of the DPLL has changed. An external pull-up resistor MUST hold this pin at HIGH level. Device Reset (5 V-Tolerant Input with Internal Pull-up) This input (active LOW) puts the device in its reset state that disables the STio0 - 31 drivers and drives the STOHZ0 - 15 outputs to high. It also preloads registers with default values and clears all internal counters. To ensure proper reset action, the reset pin must be low for longer than 1s. Upon releasing the reset signal to the device, the first microprocessor access cannot take place for at least 600s due to the time required to stabilize the device and the crystal oscillator from the power-down state. Refer to Section Section 17.2 on page 47 for details.
P10
43
IRQ
G2
211
RESET
3.0
Device Overview
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31). STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking digital switch with 4096 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15). By using Zarlink's message mode capability, microprocessor data stored in the connection memory can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS/GCI-Bus devices. The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The output data streams will be driven by and have their timing defined by FPi and CKi in Divided Slave mode. In Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied from CKi internally. In Master mode, the on-chip DPLL will drive the output data streams and provide output clocks and frame pulses. Refer to Application Note ZLAN-120 for further explanation of the different modes of operation. When the device is in Master mode, the DPLL is phase-locked to one of four DPLL reference signals, REF0 - 3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 4E specification. The intrinsic jitter of all output clocks is less than 1 ns (except for the 1.544 MHz output).
20
Zarlink Semiconductor Inc.
ZL50022
There are two slave modes for this device:
Data Sheet
The first is the Divided Slave mode. In this mode, output streams are clocked by input CKi. Therefore the output streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps. For the Divided Slave mode, the core master clock can be either 98.304 MHz, which is multiplied from CKi, or 100 MHz, which is multiplied from a 20 MHz oscillator. The Divided Slave mode with 98.304 MHz core master clock is called Divided Slave with CKi mode, and the mode with 100 MHz core master clock is called Divided Slave with OSC mode. The second slave mode is called Multiplied Slave mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by this 16.384 MHz clock. In Multiplied Slave mode, the data rate of output streams can be any rate, but output jitter may not be exactly the same as input jitter. A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate in various modes under different switching configurations. Users can use the microprocessor port to perform internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY). The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
Data Rates and Timing
The ZL50022 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame. The output streams can be programmed to operate as bi-directional streams. The output streams are divided into two groups to be programmed into bi-directional mode. By setting BDL (bit 6) in the Internal Mode Selection (IMS) register, input streams 0 - 15 (STi0 - 15) are internally tied low, and output streams 0 - 15 (STio0 - 15) are set to operate in a bi-directional mode. Similarly, when BDH (bit 7) in the Internal Mode Selection (IMS) register is set, input streams 16 - 31 (STi16 - 31) are internally tied low, and output streams 16 - 31 (STio16 - 31) are set to operate in bi-directional mode. The groups do not have to be set into the same mode. Therefore it is possible to have half of the streams operating in bi-directional mode while the other half is operating in normal input/output mode. The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 31 (SICR0 - 31). The output data rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). The output data rates do not have to match or follow the input data rates.The maximum number of channels switched is limited to 4096 channels. If all 32 input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels. Memory limitations prevent the device from operating at this capacity. A maximum capacity of 4096 channels will occur if half of the total streams are operating at 16.384 Mbps or all streams are operating at 8.192 Mbps. With all streams operating at 4.096 Mbps, the switching capacity is reduced to 2048 channels. And with all streams operating at 2.048 Mbps, the capacity will be further reduced to 1024 channels. However, as each stream can be programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel count does not exceed 4096 channels. It should be noted that only full stream can be programmed for use. The device does not allow fractional streams.
4.1
External High Impedance Control, STOHZ0 - 15
There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin, OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
21
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 18 on page 34 for a diagrammatical explanation.
4.2
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The input clock for the ZL50022 can be arranged in one of three different ways. These different ways will be explained further in Section 11.1 to Section 11.3 on page 39. Depending on the mode of operation, the input clock, CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device. In Master mode and Divided Slave mode, the input clock, CKi, must be at least twice the highest input or output data rate. For example, if the highest input data rate is 4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In Master mode, CKo2 and FPo2 can be programmed to be used as CKi and FPi by setting CKi_LP (bit 10) in the Control Register (CR). This will internally loop back the CKo2 and FPo2 timing. When this bit is set, CKi and FPi must be tied low or high externally. Highest Input or Output Data Rate 16.384 Mbps or 8.192 Mbps 4.096 Mbps 2.048 Mbps
CKIN 1-0 Bits 00 01 10
Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz
Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes In Multiplied Slave mode, the input clock, CKi, must be at least twice the highest input data rate, regardless of the output data rate. Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz, regardless of the output data rate. The only exception to this is for 16.384 Mbps input data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. Highest Input Data Rate 16.384 Mbps or 8.192 Mbps 4.096 Mbps 2.048 Mbps CKIN 1-0 Bits 00 01 10 Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 2 - CKi and FPi Configurations for Multiplied Slave Mode The ZL50022 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
22
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
ST-BUS GCI-Bus
FPi (244 ns) FPINP = 0 FPINPOS = 0 FPi (244 ns) FPINP = 1 FPINPOS = 0 FPi (244 ns) FPINP = 0 FPINPOS = 1 FPi (244 ns) FPINP = 1 FPINPOS = 1 CKi (4.096 MHz) CKINP = 0 CKi (4.096 MHz) CKINP = 1 Channel 0 STi (2.048 Mbps) Channel 31
0
7
6
1
0
7
Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR
ST-BUS GCI-Bus
FPi (122 ns) FPINP = 0 FPINPOS = 0 FPi (122 ns) FPINP = 1 FPINPOS = 0 FPi (122 ns) FPINP = 0 FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Channel 63
1
0
7
6
5
4
2
1
0
7
6
Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR
23
Zarlink Semiconductor Inc.
ZL50022
ST-BUS FPi (61 ns) FPINP = 0 FPINPOS = 0 FPi (61 ns) FPINP = 1 FPINPOS = 0 FPi (61 ns) FPINP = 0 FPINPOS = 1 GCI-Bus FPi (61 ns) FPINP = 1 FPINPOS = 1 CKi (16.384 MHz) CKINP = 0 CKi (16.384 MHz) CKINP = 1 Channel 0 STi (8.192 Mbps) STi (16.384 Mbps) Channel N = 127
Data Sheet
107654 321
Channel 0
54 3 2 1 0 7 65
Channel N = 255
321076543210765432
321076543210765432
Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR
5.0
ST-BUS and GCI-Bus Timing
The ZL50022 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge of CKo while FPo goes high. The data rates define the number of channels that are available in a 125 s frame pulse period. By default, the ZL50022 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the polarity (positive-going or negative-going) of the output clocks.
6.0
Output Timing Generation
The ZL50022 generates frame pulse and clock timing. There are five output frame pulse pins (FPo0 - 3, 5) and six output clock pins (CKo0 - 5). All output frame pulses are 8 kHz output signals. By default, the output frame boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1, CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. At the output frame boundary, CKo4 will by default have a falling edge while FPo0 is low (CKo4 has no corresponding output frame pulse). At the output frame boundary, CKo5 will by default have a rising edge while FPo5 (FPo_OFF2) will be low. The duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 3 on page 25. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode Selection (IMS) register.
24
Zarlink Semiconductor Inc.
ZL50022
Pin Name FPo0 pulse width CKo0 FPo1 pulse width CKo1 FPo2 pulse width CKo2 FPo3 pulse width CKo3 CKo4 FPo5 pulse width CKo5 Output Timing Rate 244 4.096 122 8.192 61 16.384 244, 122, 61 or 30 4.096, 8.192, 16.384 or 32.768 1.544 or 2.048 51 19.44 Table 3 - Output Timing Generation Output Timing Unit ns MHz ns MHz ns MHz ns MHz MHz ns MHz
Data Sheet
The output timing is dependent on the operation mode that is selected. When the device is in Divided Slave mode, the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is 8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output a 4.096 MHz or 8.192 MHz clock signal. The output clocks CKo4 - 5 will not generate valid outputs unless the SLV_DPLLEN (bit 13) of the Control Register (CR) is set. In Master mode there are programmable output frame pulse, FPo3, and clock pins, CKo3 and CKo4. The outputs from FPo3 and CKo3 are programmed by the CKOFPO3SEL1 - 0 (bits 13 - 12) in the Output Clock and Frame Pulse Selection (OCFSR) register. The output clock pin, CKo4, is controlled by setting the CKO4SEL (bit 14) in the OCFSR register. In Multiplied Slave mode, CKo4 and CKo5 are not available unless SLV_DPLLEN is set in the Control Register. All other clocks and frame pulses correspond to the timing shown in Table 3 above. The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the device delivers the negative output clock format. The ZL50022 can also deliver GCI-Bus format output frame pulses by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in GCI-Bus mode. The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P, CKO3P, CKO4P and CKO5P bits to generate the FPo0 - 3 and CKo0 - 5 timing. FPo_OFF2 is configured to provide the non-offset frame pulse corresponding to the 19.44 MHz clock on CKo5 by setting the FP19EN (bit 10) in the FPOFF2 register. In this instance, FPo_OFF2 can be labeled as FPo5.
25
Zarlink Semiconductor Inc.
ZL50022
ST-BUS CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 1 GCI-Bus CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 1 CKOFPO0EN = 1 CKO0P = 0 CKo0 = 4.096 MHz CKOFPO0EN = 1 CKO0P = 1 CKo0 = 4.096 MHz
Data Sheet
Figure 7 - Output Timing for CKo0 and FPo0
ST-BUS GCI-Bus
CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz
Figure 8 - Output Timing for CKo1 and FPo1
26
Zarlink Semiconductor Inc.
ZL50022
ST-BUS CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 1 GCI-Bus CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 1
Data Sheet
CKOFPO2EN = 1 CKO2P = 0 CKo2 = 16.384 MHz CKOFPO2EN = 1 CKO2P = 1 CKo2 = 16.384 MHz
Figure 9 - Output Timing for CKo2 and FPo2
CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 0 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 1 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 0 FPO3POS = 1 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 1 FPO3POS = 1 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 CKO3P = 0 CKo3 = 32.768 MHz CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 CKO3P = 1 CKo3 = 32.768 MHz
GCI-Bus
ST-BUS
NOTE: When CKOFPO3SEL1-0 = "00," the output for FPo3 and CKo3 follow the same as Figure 7: Output Timing for CKo0 and FPo0 When CKOFPO3SEL1-0 = "01," the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = "10," the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2
Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0="11"
27
Zarlink Semiconductor Inc.
ZL50022
ST-BUS CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 1 GCI-Bus CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 1 CKOFPO4EN = 1 CKO4P = 0 CKO4SEL = 0 CKo4 = 2.048 MHz CKO4EN = 1 CKO4P = 1 CKO4SEL = 0 CKo4 = 2.048 MHz CKOFPO4EN = 1 CKO4P = 0 CKO4SEL = 1 CKo4 = 1.544 MHz CKO4EN = 1 CKO4P = 1 CKO4SEL = 1 CKo4 = 1.544 MHz
Data Sheet
Note: While there is no frame pulse output directly tied to the CKo4, the output clocks are based on the frame pulse generated by FPo0
Figure 11 - Output Timing for CKo4
FPo5 (FPo_OFF2) FP19EN = 1
CKO5EN = 1 CK5 = 19.44 MHz
Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2)
28
Zarlink Semiconductor Inc.
ZL50022
7.0 Data Input Delay and Data Output Advancement
Data Sheet
Various registers are provided to adjust the input delay and output advancement for each input and output data stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream. If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate. The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2 bit. By default, there is 0 output bit advancement. Although input delay or output advancement features are available on streams which are operating in bi-directional mode it is not recommended, as it can easily cause bus contention. If users require this function special, attention must be given to the timing to ensure contention is minimized.
7.1
Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream Input Control Register 0 - 31 (SICR0 - 31) as described in Table 45 on page 79. The input bit delay can range from 0 to 7 bits.
FPi Last Channel STi[n] Bit Delay = 0 (Default) Channel 0 Channel 1 Channel 2
432107654321076543210765432
Bit Delay = 1 Last Channel Channel 2
STi[n] Bit Delay = 1
Channel 0
Channel 1
543210765432107654321076543
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 13 - Input Bit Delay Timing Diagram (ST-BUS)
29
Zarlink Semiconductor Inc.
ZL50022
7.2 Input Bit Sampling Point Programming
Data Sheet
In addition to the input bit delay feature, the ZL50022 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
FPi Sampling Point = 3/4 Bit Channel 0
STi[n] STIN[n]SMP1-0 = 00 (2, 4 or 8 Mbps Default) STi[n] STIN[n]SMP1-0 = 01 (2, 4 or 8 Mbps) STi[n] STIN[n]SMP1-0 = 10 (2, 4 or 8 Mbps) STIN[n]SMP1-0 = 00 (16 Mbps - Default) STi[n] STIN[n]SMP1-0 = 11 (2, 4 or 8 Mbps) STIN[n]SMP1-0 = 10 (16 Mbps)
Last Channel
2
1
0
7
6
Sampling Point = 1/4 Bit Channel 0
5
Last Channel
1
0
Last Channel
7
6
5
Sampling Point = 1/2 Bit Channel 0
1
Last Channel
0
7
6
5
Sampling Point = 4/4 Bit Channel 0
2
1
0
7
6
5
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 14 - Input Bit Sampling Point Programming
30
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
Nominal Channel n Boundary Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7 111 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01
000 01 000 10 000 00 (Default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)
Figure 15 - Input Bit Delay and Factional Sampling Point
31
Zarlink Semiconductor Inc.
ZL50022
7.3 Output Advancement Programming
Data Sheet
This feature is used to advance the output data of individual output streams with respect to the output frame boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output Control Register 0 - 31 (SOCR0 - 31). By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4) of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 47 on page 83. The output bit advancement can vary from 0 to 7 bits.
FPi Channel 2
Last Channel STio[n] Bit Adv = 0 (Default)
Channel 0
Channel 1
432107654321076543210765432
Bit Advancement = 1 Last Channel Channel 0 Channel 1 Channel 2
STio[n] Bit Adv = 1
321076543210765432107654321
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)
32
Zarlink Semiconductor Inc.
ZL50022
7.4 Fractional Output Bit Advancement Programming
Data Sheet
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the fractional bit advancement can be set to either 0 or 1/2 bit.
FPi
Last Channel STio[n] STo[n]FA1-0 = 00 (Default 2, 4, 8 or 16 Mb/s) STio[n] STo[n]FA1-0 = 01 (2, 4 or 8 Mbps) STio[n] STo[n]FA1-0 = 10 (2, 4 or 8 Mbps) STo[n]FA1-0 = 01 (16 Mbps)
Channel 0
2
1
Last Channel
0
7
6
Channel 0
5
Fractional Bit Advancement = 1/4 Bit
1
0
7
6
5
4
Fractional Bit Advancement = 1/2 Bit Last Channel Channel 0
1
0
7
6
5
4
Fractional Bit Advancement = 3/4 Bit STio[n] STo[n]FA1-0 = 11 (2, 4 or 8 Mbps) Last Channel Channel 0
1
0
7
6
5
4
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
33
Zarlink Semiconductor Inc.
ZL50022
7.5 External High Impedance Control Advancement
Data Sheet
The external high impedance signals can be programmed to better match the timing required by the external buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at 16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same register.
FPi HiZ STio[n] Last CH0 CH1 CH2 CH3 Last-2 Last-1 Last CH0
STOHZ Advancement (Programmable in 4 steps of 1/4 bit for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps Programmable in 2 steps of 1/2 bit for 16.384 Mbps) STOHZ[n] (Default = No Advancement) STOHZ[n] (with Advancement) Output Frame Boundary Note: n = 0 to 15 Note: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.
Figure 18 - Channel Switching External High Impedance Control Timing
8.0
Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
8.1
Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for voice applications where the minimum throughput delay is more important than frame integrity. The delay through the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN (bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid.
34
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. m = input channel number n = output channel number T = Delay between input and output n-m <= 0 1 frame - (m-n) 0 < n-m < 7 STio < STi 1 frame + (n-m) Table 4 - Delay for Variable Delay Mode For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in the same 125 s frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will appear in the following frame.
Frame N Frame N + 1
n-m = 7 STio >= STi n-m
n-m > 7
STi4 CH2
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio5 CH9
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STi6 CH1
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio9 CH3
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 19 - Data Throughput Delay for Variable Delay
8.2
Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all output channels. The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and output channel number (n). The data throughput delay (T) is: T = 2 frames + (n - m) The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode.
35
Zarlink Semiconductor Inc.
ZL50022
Frame N Frame N + 1
Data Sheet
Frame N + 2
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, or 16.384 Mbps respectively
Figure 20 - Data Throughput Delay for Constant Delay
9.0
Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High (CM_H). The CM_L is 16-bits wide and is used for channel switching and other special modes. The CM_H is 5 bits wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low, -law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory location of the CM_L or CM_H can be read or written via the 16-bit microprocessor port within one microprocessor access cycle. See Table 52 on page 86 for the address mapping of the connection memory. Any unused bits will be reset to zero on the 16-bit data bus. For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source (input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode without the -law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If -law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information, the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory Low. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50022 will operate in one of the special modes described in Table 54 on page 88. When the per-channel message mode is enabled, MSG7 - 0 (bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data. When the per-channel message mode is enabled, the -law/A-law conversion can also be enabled as required.
36
Zarlink Semiconductor Inc.
ZL50022
10.0 Connection Memory Block Programming
Data Sheet
This feature allows for fast initialization of the connection memory after power up.
10.1
Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded into CM_L. 3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The values stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15 - 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values. The following tables show the resulting values that are in the CM_L and CM_H connection memory locations. Bit Value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 BPD2 1 BPD1 0 BPD0
Table 5 - Connection Memory Low After Block Programming
Bit Value
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Table 6 - Connection Memory High After Block Programming Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0. It takes at least two frame periods (250 s) to complete a block program cycle. MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming process has completed. MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block programming process. This is not an automatic action taken by the device and must be performed manually. Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other device operations.
11.0
Device Operation in Master Mode and Slave Modes
This device has two main operating modes - Master mode and Slave mode. Each operating mode has different input/output clock and frame pulse setup requirements and usage. If the device is programmed to work in Master mode, it is expected that the input clock and frame pulse will be supplied from the embedded DPLL, either directly using the internal loopback mode or indirectly through external loopback path. Sources and destinations of the device's serial input and output data, respectively, have to be synchronized with the device's output clock and frame pulse. In Master mode, output clocks and frame pulses are driven by the DPLL and they are always available with any of the specified frequencies. The device can also operate in two different Slave modes: Divided Slave mode and Multiplied Slave mode. In either Slave modes, output clocks and frame pulses are generated based on CKi and FPi. The difference is that, in
37
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
Divided Slave mode, the output clocks and frame pulses are directly divided from CKi/FPi, while in Multiplied Slave mode, the output clocks and frame pulses are generated from an internal high-speed clock synchronized to CKi and FPi. Therefore, in Divided Slave mode, the output clock rates cannot exceed the CKi rate (the output data rates are also limited as per Table 1), but in Multiplied Slave mode, all specified output clock rates and data rates are available on CKo0-3 and STio0-31. The input data rate cannot exceed the CKi rate in either Slave modes, because input data are always sampled directly by CKi. By default, CKo4, CKo5 and FPo5 are not available in Slave mode, as the embedded DPLL is disabled. However, the DPLL can be activated even in Slave mode by programming the SLV DPLLEN bit in the Control Register. When the DPLL is enabled in Slave mode, CKo4, CKo5 and FPo5 are generated from the DPLL synchronized to one of the REF0-3 inputs, while the other clocks, frame pulses, and input/output data are synchronized to CKi/FPi. It basically creates two separate timing domains - one for the DPLL, and one for data switch logic. The two can be totally asynchronous to each other. In this case the DPLL will be fully functional, including its capability of reference monitoring. Note that an external oscillator is required whenever the DPLL is used. Table 7, "ZL50022 Operating Modes" on page 38 summarizes the different modes of operation available within the ZL50022. Each Major mode has various associated Minor modes that are determined by setting the relevant Input Control pins and Control Register bits (Table 17, "Control Register (CR) Bits" on page 53) indicated in the table.
Device Operating Mode Major Master Minor CKi Loopback Divided Slave 4M 8/16 M 4M 8/16 M Multiplied Slave 4M 8/16 M 4M 8/16 M Legend: X - Don't care or not applicable. Reference Lock - Refers to what signal the output pins are locked to: REF0-3 = Normal Mode Cki = Bypass. Cki is passed directly through to CKo0-3. Cki MULT = Cki is passed through clock multiplier to CKo0-3. * CKi must be phase aligned (edge synchronous) to CKo0-3. Clock Source - Refers to which clock samples STi and which clock outputs STo; STi applies when STi or STio is input; STo applies when STio is output. 0 1 0 1 11 00 11 00 11 00 11 00 X 20 MHz X 20 MHz Control OSC_EN MODE_4M [1:0] 1 00 Input Pins Signal OSCi CKi OPM [1:0] 00 CR Register Bits SLV_DPLLEN X CKi_LP 0 1 01 1 X Output Clock Pins Reference Lock CKo0-3 Enabled Data Pins Clock Source STi CKi* Cko2 Yes CKi STo Cko2 (DPLL) CKo0-3 (CKi)
CKo4-5 CKo0-3 CKo4-5 Yes Yes
20 MHz 4/8/16 M X 4M 8/16 M 4M 8/16 M 4M 8/16 M 4M 8/16 M
Freerun, Holdover or REF0-3 CKi REF0-3
X0
0
X
No
11
1
CKi MULT REF0-3
Yes
CKo0-3 (CKi MULT)
X1
0
X
No
Table 7 - ZL50022 Operating Modes
11.1
Master Mode Operation
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and holdover functions. In this mode, STio0 - 31 are driven by a clock generated by the DPLL, which also provides all the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2). One of the output clocks and frame pulses should be looped back to CKi/FPi as reference for the input data, either by internal loopback (by setting the CKi_LP bit high in the Control Register) or through some external loopback paths. If external loopback is used, it is recommended that CKo2 (16.384MHz) and FPo2 (61ns pulse) are used so that all input data rates are available.
38
Zarlink Semiconductor Inc.
ZL50022
11.2 Divided Slave Mode Operation
Data Sheet
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and clocks have the same jitter characteristics as the input clock (CKi), but the input and output data rates cannot exceed the limit defined by CKi (as per Table 1). For example, if CKi is 4.096 MHz, the input and output data rate cannot be higher than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is not enabled, an external oscillator is optional in Divided Slave mode.
11.3
Multiplied Slave Mode Operation
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are driven by this internally generated clock. In this mode, the output clocks and data can run at any of the specified rates, but they may have different jitter characteristics from the input clock (CKi). The input data rates are still limited by the CKi rate (as per Table 1), as input data are always sampled directly by CKi. If the DPLL is not enabled, an external oscillator is not required in Multiplied Slave mode.
12.0
Overall Operation of the DPLL
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 4E compliant PLL. This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover functions. The intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output). The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
12.1
DPLL Timing Modes
There are four timing modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these four functional timing modes, the DPLL can also be programmed to internal reset mode.
12.1.1
Normal Mode
In normal timing mode, the DPLL generates clocks and frame pulses that are phase locked to the active input reference. Jitter on the input clock is attenuated by the DPLL.
12.1.2
Holdover Mode
In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the frequency that it was at prior to entering holdover mode. The holdover mode typically happens when the input clock becomes unreliable or is lost altogether. It takes some time for the system to realize that the input clock is unreliable. Meanwhile, the DPLL tracks an unreliable clock. Therefore the DPLL could hold to an invalid frequency when it enters holdover mode. In order to prevent this situation, the DPLL stores the current frequency at regular intervals in holdover memory so that it can restore the frequency of the input clock just after the input clock became unreliable.
12.1.3
Automatic Mode
In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the reference input clocks. The DPLL is internally either in normal or holdover mode. In the following two sections, the reference selection and state machine operation in automatic mode will be explained in more details.
39
Zarlink Semiconductor Inc.
ZL50022
12.1.3.1 Automatic Reference Switching Without Preferences
Data Sheet
When the DPLL is programmed to operate in Automatic mode without Preference (RCCR Register, PMS2-0 bits = 000), all references, REF0-3, will have equal importance. A circulating Round Robin selection sequence determines the reference to be used as shown in Figure 21. The state machine basically searches for valid reference in a circular order of REF0 -> REF1 -> REF2 -> REF3 -> REF0, etc.
Free run Ref 1 valid
0 ef dR n da ali 1v
Ref 0 failed Ref 0 Ref 0 valid
0 ef R lid va d an f3 Re d ile fa
f Re
Holdover 0
Ref 3 and 0 failed and (Ref 1 or Ref 1 valid)
Ref 0 and 1 failed and (Ref 2 or Ref 3 valid)
Holdover 1
2 ef R
Ref 1 and 2 failed and (Ref 3 or Ref 0
All Ref failed
All Ref failed
Ref 1 failed
Start
led fai
Ref 1
lid va d an 1 ef R
All Ref failed
All Ref failed
valid)
d ile fa
Holdover 3 Ref 3 failed Ref 3 valid
Ref 2 and 3 failed and (Ref 0 or Ref 1 valid)
Ref 2 valid Holdover 2 Ref 2 failed
Ref 2
Ref 3
f Re
f2 Re d an lid a 3v
led fai
Figure 21 - Automatic Reference Switching State Diagram with No Preferred Reference
40
Zarlink Semiconductor Inc.
ZL50022
12.1.3.2 Automatic Reference Switching With Preferences
Data Sheet
If a particular reference needs to have higher priority than the others, the device can be programmed in Automatic mode with a preferred reference (RCCR Register, PMS2-0 bits = 001). When a preferred reference is selected, the device can only switch automatically between two references, as shown in Table 8. The preferred reference will be used as the primary reference and, by default, only its next consecutive reference will be used as the secondary reference. No more than two references can be used in Automatic mode when a preferred reference is selected. Primary Reference (Preferred) Option 1 Option 2 Option 3 Option 4 Ref 0 Ref 1 Ref 2 Ref 3 Table 8 - Preferred Reference Selection Options Figure 22 shows the state diagram for the four valid options of automatic reference switching with a preferred reference. Secondary Reference Ref 1 Ref 2 Ref 3 Ref 0
41
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
Option 1 Start Free run
Ref 0 and 1 failed Holdover 0
Ref 1 v
Ref 0 valid
Ref 0 failed alid a nd Re f 0 fa Ref 0 and 1 failed iled Ref 1 failed or Ref 0 valid Ref 1 valid and Ref 0 failed
Preferred Ref 0
Preferred References : Ref 0 DPLL will switch between Ref 0 and Ref 1 Option 2 Free run Start
Holdover 1
Ref 1
Ref 0 valid
Ref 1 and 2 failed Holdover 1
R ef 2
Ref 1 valid Ref 1 failed
nd R ef 1 f ailed
Preferred Ref 1
valid a
Ref 1 and 2 failed Preferred References : Ref 1 DPLL will switch between Ref 1 and Ref 2 Option 3 Free run Start Holdover 2
Ref 2 failed or Ref 1 valid Ref 2 valid and Ref 1 failed
Ref 2
Ref 1 valid
Ref 2 and 3 failed Holdover 2
Re f 3
Ref 2 valid
Ref 2 failed v a lid and Re f 2 failed Ref 2 and 3 failed Ref 3 failed or Ref 2 valid Ref 3 valid and Ref 2 failed Ref 2 valid
Preferred Ref 2
Preferred References : Ref 2 DPLL will switch between Ref 2 and Ref 3 Option 4 Free run Start
Holdover 3
Ref 3
Ref 0 and 3 failed Holdover 3
Ref 3 valid
Ref Ref 3 failed 0 va lid a nd R Ref 0 and 3 failed ef 3 faile d
Preferred Ref 3
Preferred References : Ref 3 DPLL will switch between Ref 3 and Ref 0
Holdover 0
Ref 0 failed or Ref 3 valid Ref 0 valid and Ref 3 failed
Ref 0
Ref 3 valid
Note : other combinations not shown here are invalid settings and should not be used Figure 22 - Automatic Reference Switching State Diagrams with Preferred Reference
42
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
With a preferred reference, if more than two references are required, or the two references are not in consecutive order, or the roles of the two references need to be interchanged, then external software is required to manually control the reference switching of the DPLL (by monitoring the reference failure status and reprogramming the device accordingly).
12.1.4
Freerun Mode
In freerun mode, the DPLL generates a fixed output frequency based on the crystal oscillator frequency. To meet Stratum 4E, the accuracy of the circuitry for the freerunning output clock must be 32 ppm or better.
12.1.5
DPLL Internal Reset Mode
DPLL_IRM (bit 0) in the DPLL Control Register (DPLLCR) enables the internal reset mode. In the internal reset mode, the DPLL module is disabled to save power. The circuit will be reset continuously and no output clocks will be generated. When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to entering reset.
13.0
13.1
DPLL Frequency Behaviour
Input Frequencies
The DPLL is able to synchronize to one of the following input frequencies: 8 kHz 1.544 MHz (DS1) 2.048 MHz (E1) 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Table 9 - DPLL Input Reference Frequencies
13.2
Input Frequencies Selection
The input frequencies of REF 0 - 3 can be automatically detected or programmed independently by the Reference Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency of the selected reference is indicated in the Reference Change Status Register (RCSR). In addition, the detected frequencies of all four references are indicated in the Reference Frequency Status Register (RFSR). See Table 28 on page 63, Table 29 on page 64, Table 37 on page 70 and Table 43 on page 77 for the detailed bit description of the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register (RCSR) and Reference Frequency Status Register (RFSR), respectively.
13.3
Output Frequencies
The DPLL generates a limited number of output signals. All signals are synchronous to each other and in the normal operating mode, are locked to the selected input reference. The DPLL provides outputs with the following frequencies:
43
Zarlink Semiconductor Inc.
ZL50022
CKo0 CKo1 CKo2 CKo3 CKo4 CKo5 FPo0 FPo1 FPo2 FPo3 FPo5 4.096 MHz 8.192 MHz 16.384 MHz 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz 1.544 MHz or 2.048 MHz 19.44 MHz 8 kHz (244 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (61 ns wide pulse) 8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse) 8 kHz (51 ns wide pulse) Table 10 - Generated Output Frequencies
Data Sheet
13.4
Pull-In/Hold-In Range (also called Locking Range)
The widest tolerance required for any of the given input clock frequencies is 130 ppm for the T1 clock (1.544 MHz). If the system clock (crystal/oscillator) accuracy is 30 ppm, it requires a minimum pull-in range of 160 ppm.Users who do not require the 30 ppm freerun accuracy of the DPLL can use a 100 ppm system clock. Therefore the pull-in range is a minimal 230 ppm. The pull-in range of this device is 260 ppm.
14.0
14.1
Jitter Performance
Input Clock Cycle to Cycle Timing Variation Tolerance
The ZL50022 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50022 to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
14.2
Input Jitter Acceptance
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is 1023UIp-p.
14.3
Jitter Transfer Function
The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz.
15.0
15.1
DPLL Specific Functions and Requirements
Lock Detector
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase detector, which represents the difference between input reference and output feedback clock. If the phase value is below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is done in intervals of 4 ms. The lock detector threshold and the interval are programmable by the user through the Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See Table 33 on page 67 and Table 34 on page 68 for the bit descriptions of the Lock Detector Threshold Register (LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
44
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the selected input references. The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 37 on page 70 for the bit description of the Reference Change Status Register (RCSR).
15.2
Maximum Time Interval Error (MTIE)
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during rearrangements is less than 31 ns per rearrangement, exceeding Stratum 4E requirements. After a large number of reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 36 on page 69.
15.3
Phase Alignment Speed (Phase Slope)
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as described in Table 35 on page 68. Stratum 4E requires that the phase alignment speed not exceed 81 ns per 1.326 ms (61ppm). The width of the register and the limiter circuitry provide a maximum phase change alignment speed of 186 ppm. The phase alignment speed default value is 56 ppm.
15.4
Reference Monitoring
The quality of the four input reference clocks is continuously monitored by the reference monitors. There are separate reference monitor circuits for the four DPLL references. References are checked for short phase (single period) deviations as well as for frequency (multi-period) deviations with hysteresis. The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described in Table 41 on page 74. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the reference monitors. See Table 42 on page 75 for details.
15.5
Single Period Reference Monitoring
Values for short phase deviations (upper and lower limit) are programmable through registers. The unit of the binary values of these numbers is 100 MHz clock period (10 ns). Single period deviation limits are more relaxed than multi period limits, and are used for early detection of the reference loss, or huge phase jumps. The values for the upper and lower limits are shown in the following table: Reference Frequency 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Comment 10UIp-p 0.3UIp-p 0.2UIp-p 0.2UIp-p 0.2UIp-p 0.2UIp-p 0.2UIp-p
Table 11 - Values for Single Period Limits
45
Zarlink Semiconductor Inc.
ZL50022
15.6 Multiple Period Reference Monitoring
Data Sheet
To monitor reference failure based on frequency offset, multi-period checking is performed. Reference validation time is prescribed by Telcordia GR-1244-CORE and is between 10 and 30 seconds. To meet the criteria for reference validation time, the time base for multi period monitoring has to be big enough. To implement hysteresis, the upper limits are split into near upper and far upper limits and the lower limits are split into near lower and far lower limits. The reference failure is detectable only when the reference passes far limits, but passing is not detected until the reference is within near limits. The zone between near and far limits, called the "grey zone", is required by standards and prevents unnecessary reference switching when the selected reference is close to the boundary of failure. The monitor makes a decision about reference validity after two consecutive measurements with respect to its time base. The time base for multi-period monitoring is 10 seconds. The time base is defined in the number of reference clock cycles. The device has two sets of limits, the Stratum 4E default limits and the Relaxed Stratum 4E limits (see Table 12, "Multi-period Hysteresis Limits" on page 46). The ST4_LIM bit in Table 28, DPLL Control Register (DPLLCR) Bits is used to select between the two sets of limits.
Stratum 4E Default Limits (in 10 ns units) Relaxed Stratum 4E Limits (in 10 ns units)
Far Upper Limit Near Upper Limit Nominal Value Near Lower Limit Far Lower Limit
-82.487 ppm -64.713 ppm 0 ppm 64.713 ppm 82.487 ppm
-250 ppm -240 ppm
240 ppm 250 ppm
Table 12 - Multi-period Hysteresis Limits
16.0
Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY). The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be used and D15 - 8 will output zeros. For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros. Refer to Figure 26 on page 94, Figure 27 on page 95, Figure 28 on page 96 and Figure 29 on page 97 for the microprocessor timing.
17.0
* * *
Device Reset and Initialization
The RESET pin is used to reset the ZL50022. When this pin is low, the following functions are performed: synchronously puts the microprocessor port in a reset state tristates the STio0 - 31 outputs drives the STOHZ0 - 15 outputs to high
46
Zarlink Semiconductor Inc.
ZL50022
* * clears all internal counters
Data Sheet
preloads all internal registers with their default values (refer to the individual registers for default values)
17.1
Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time as VDD_IO, but should not "lead" the VDD_IO supply by more than 0.3 V.
17.2
Device Initialization on Reset
Upon power up, the ZL50022 should be initialized as follows: * * * * * * * * Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high Set the TRST pin to low to disable the JTAG TAP controller Reset the device by pulsing the RESET pin to zero for longer than 1 s After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the device to stabilize from the power down state before the first microprocessor port access can occur Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs Wait at least 500 s prior to the next microport access (see Note below) Use the block programming mode to initialize the connection memory Release the ODE pin from low to high after the connection memory is programmed
Note: If an external oscillator is used, the waiting time is 500 s. Without the external oscillator, if CKi is 16.384 MHz, the waiting time is 500 s; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the waiting time is 2 ms.
17.3
Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while SRSTSW (bit 1) resets the rest of the switch.
18.0
Pseudo-random Bit Generation and Error Detection
The ZL50022 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudo-random code (ITU O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 s). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled. (This is the default state.) Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how many BER channels are to be monitored by the BER receiver. For each input stream, there is a set of registers for the BER test. The registers are as follows: * BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register (BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
47
Zarlink Semiconductor Inc.
ZL50022
* *
Data Sheet
BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the BER sequence will start to be compared. BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256 channels at the data rates of 2.048, 4.096, 8.192 or 16.384 Mbps, respectively. The minimum length of the BER test is a single channel. The user must take care to program the correct channel length for the BER test so that the channel length does not exceed the total number of channels available in the stream. BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER (bit 1) in the BER Receiver Control Register is used to reset the BRER register.
*
For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L). PCC1 - 0 (bits 2 - 1) in the Connection Memory Low must be programmed to "10" to enable the per-stream based BER transmitters. For each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 s) between completion of connection memory programming and starting the BER receiver before the BER receiver can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.
19.0
PCM A-law/-law Translation
The ZL50022 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode and Message Mode. In order to use this feature, the Connection Memory High (CM_H) entry for the output channel must be programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 13. The different code options are: Input Coding (ICL1- 0) 00 01 10 11 Output Coding (OCL1 - 0) 00 01 10 11 Voice Coding (V/D bit = 0) ITU-T G.711 A-law ITU-T G.711 -law A-law without Alternate Bit Inversion (ABI) -law without Magnitude Inversion (MI) Data Coding (V/D bit = 1) No code Alternate Bit Inversion (ABI) Inverted Alternate Bit Inversion (ABI) All bits inverted
Table 13 - Input and Output Voice and Data Coding For voice coding options, the ITU-T G.711 A-law and ITU-T G.711 -law are the standard rules for encoding. A-law without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). -law without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3, 2, 1, 0). When transferring data code, the option "no code" does not invert the bits. The Alternate Bit Inversion (ABI) option inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When the "All bits inverted" option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted. The input channel and output channel encoding law are configured independently. If the output channel coding is set to be different from the input channel, the ZL50022 performs translation between the two standards. If the input
48
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data encoding laws.
20.0
Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or zero for robbed-bit signaling. The four quadrant frames are defined as follows: Data Rate 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Quadrant 0 Channel 0 - 7 Channel 0 - 15 Channel 0 - 31 Channel 0 - 63 Quadrant 1 Channel 8 - 15 Channel 16 - 31 Channel 32 - 63 Channel 64 - 127 Quadrant 2 Channel 16 - 23 Channel 32 - 47 Channel 64 - 95 Channel 128 - 191 Quadrant 3 Channel 24 - 31 Channel 48 - 63 Channel 96 - 127 Channel 192 - 255
Table 14 - Definition of the Four Quadrant Frames When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit 5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to "1" or "0" as shown by the following table: STIN[n]Q[y]C[2:0] 0xx 100 101 110 111 Note: y = 0, 1, 2, 3 Table 15 - Quadrant Frame Bit Replacement Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input stream. Normal Operation Replaces LSB of every channel in Quadrant y with `0' Replaces LSB of every channel in Quadrant y with `1' Replaces MSB of every channel in Quadrant y with `0' Replaces MSB of every channel in Quadrant y with `1' Action
21.0
JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
21.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50022 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic.
49
Zarlink Semiconductor Inc.
ZL50022
*
Data Sheet
Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. The registers are described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo driver is set to a high impedance state. Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not driven from an external source.
*
*
*
21.2
Instruction Register
The ZL50022 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning.
21.3
Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50022 JTAG interface contains three test data registers: * * * The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the ZL50022 core logic. The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from TDi to TDo. The Device Identification Register - The JTAG device ID for the ZL50022 is 0C36614BH Version Part Number Manufacturer ID LSB <31:28> <27:12> <11:1> <0> 0000 1100 0011 0110 0110 0001 0100 101 1
21.4
BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE-1149.1 test interface.
50
Zarlink Semiconductor Inc.
ZL50022
22.0 Register Address Mapping
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W R Only R Only R Only R Only R Only R/W R/W R/W R/W R Only R/W R/W R/W R/W R Only R Only R/W R/W R Only R/W R Only R/W Control Register Internal Mode Selection Register Software Reset Register Output Clock and Frame Pulse Control Register Output Clock and Frame Pulse Selection Register FPo_OFF0 Register FPo_OFF1 Register FPo_OFF2 Register Internal Flag Register BER Error Flag Register 0 BER Error Flag Register 1 BER Receive Lock Register 0 BER Receive Lock Register 1 DPLL Control Register Reference Frequency Register Centre Frequency Register - Lower 16 Bits Centre Frequency Register - Upper 10 Bits Frequency Offset Register Lock Detector Threshold Register Lock Detector Interval Register Slew Rate Limit Register Reference Change Control Register Reference Change Status Register Interrupt Register Interrupt Mask Register Interrupt Clear Register Reference Failure Status Register Reference Mask Register Reference Frequency Status Register Output Jitter Control Register Register Name Abbreviation CR IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERFR1 BERLR0 BERLR1 DPLLCR RFR CFRL CFRU FOR LDTR LDIR SRLR RCCR RCSR IR IMR ICR RSR RMR RFSR OJCR
Data Sheet
Address A13 - A0 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0010H 0011H 0012H 0013H 0014H 0040H 0041H 0042H 0043H 0045H 0047H 0048H 0049H 004BH 004CH 0066H 0067H 0068H 0069H 006AH 006BH 006CH
Reset By Switch/Hardware Switch/Hardware Hardware Only DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware
Table 16 - Address Map for Registers (A13 = 0)
51
Zarlink Semiconductor Inc.
ZL50022
Address A13 - A0 0100H 011FH 0120H 013FH 0200H 021FH 0300H 031FH 0320H 033FH 0340H 035FH 0360H 037FH CPU Access R/W R/W R/W R/W R/W R/W R Only Register Name Stream Input Control Registers 0 - 31 Stream Input Quadrant Frame Registers 0 - 31 Stream Output Control Registers 0 - 31 BER Receiver Start Registers 0 - 31 BER Receiver Length Registers 0 - 31 BER Receiver Control Registers 0 - 31 BER Receiver Error Registers 0 - 31 Abbreviation SICR0 - 31 SIQFR0 - 31 SOCR0 - 31 BRSR0 - 31 BRLR0 - 31 BRCR0 - 31 BRER0 - 31
Data Sheet
Reset By Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware
Table 16 - Address Map for Registers (A13 = 0) (continued)
52
Zarlink Semiconductor Inc.
ZL50022
23.0 Detailed Register Description
Data Sheet
External Read/Write Address: 0000H Reset Value: 0000H 15
0
14
0
13
SLV_ DPLLEN
12
OPM 1
11
OPM 0
10
CKi_ LP
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 15 - 14 13
Name Unused SLV_ DPLLEN
Description Reserved. In normal functional mode, these bits MUST be set to zero. DPLL Enable in Slave Mode (Ignored in Master Mode). When this bit is low, DPLL is disabled in Slave mode. When this bit is high and OSC_EN = 1, the DPLL is enabled in Slave mode. When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the generation of the REF_FAIL[3:0] output signals. See Table 7, "ZL50022 Operating Modes" on page 38 for more details. Operation Mode. These bits are used to set the device in Master/Slave operation. Refer to Table 7, "ZL50022 Operating Modes" on page 38 for more details. CKi and FPi Loopback (Ignored in slave mode) When this bit is low, CKi and FPi are used as input pins. When this bit is high, CKi and FPi are internally looped back from CKo2 (16.384 MHz) and FPo2 respectively, and CKi pin and FPi pin should be tied low or high externally; CKIN1 - 0 (bits 6 - 5) of this register should be programmed to be 00. See Table 7, "ZL50022 Operating Modes" on page 38 for more details. Input Frame Pulse (FPi) Position When this bit is low, FPi straddles frame boundary (as defined by ST-BUS). When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus) Clock Input (CKi) Polarity When this bit is low, the CKi falling edge aligns with the frame boundary. When this bit is high, the CKi rising edge aligns with the frame boundary. Frame Pulse Input (FPi) Polarity When this bit is low, the input frame pulse FPi has the negative frame pulse format. When this bit is high, the input frame pulse FPi has the positive frame pulse format. Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0 00 01 10 11 FPi Active Period 61 ns 122 ns 244 ns Reserved CKi 16.384 MHz 8.192 MHz 4.096 MHz
12 - 11
OPM1 - 0
10
CKi_LP
9
FPINPOS
8
CKINP
7
FPINP
6-5
CKIN1 - 0
The MODE_4M0 and MODE_4M1 pins, as described in "Pin Description" on page 13, should also be set to define the input clock mode. Table 17 - Control Register (CR) Bits
53
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0000H Reset Value: 0000H 15
0
Data Sheet
14
0
13
SLV_ DPLLEN
12
OPM 1
11
OPM 0
10
CKi_ LP
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 4
Name VAREN
Description Variable Delay Mode Enable When this bit is low, the variable delay mode is disabled on a device-wide basis. When this bit is high, the variable delay mode is enabled on a device-wide basis. Memory Block Programming Enable When this bit is high, the connection memory block programming mode is enabled to program the connection memory. When it is low, the memory block programming mode is disabled. Output Stand By Bit: This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table describes the HiZ control of the serial data outputs:
RESET Pin 0 1 1 1 1 SRSTSW (in SRR) X 1 0 0 0 ODE Pin X X 0 1 1 OSB Bit X X X 0 1 STio0 - 31 HiZ HiZ HiZ HiZ Active (Controlled by CM) STOHZ0 - 15 Driven High Driven High Driven High Driven High Active (Controlled by CM)
3
MBPE
2
OSB
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 31 (bit2 - 0).
1-0
MS1 - 0
Memory Select Bits These two bits are used to select connection memory low, connection high or data memory for access by CPU:
MS1 - 0 00 01 10 11 Memory Selection Connection Memory Low Read/Write Connection Memory High Read/Write Data Memory Read Reserved
Table 17 - Control Register (CR) Bits (continued)
54
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0001H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 STIO_ PD_EN 7 BDH 6 BDL 5 RBER EN 4 TBER EN 3 BPD 2 2 BPD 1 1 BPD 0 0 MBPS
Bit 15 - 9 8
Name Unused STIO_PD_ EN BDH
Description Reserved. In normal functional mode, these bits MUST be set to zero. STio Pull-down Enable When this bit is low, the pull-down resistors on all STio pads will be disabled. When this bit is high, the pull-down resistors on all STio pads will be enabled. Bi-directional Control for Streams 16-31
BDH 0 STio16 - 31 Operation normal operation: STi16-31 are inputs STio16-31 are outputs bi-directional operation: STi16-31 tied low internally STio16-31 are bi-directional
7
1
6
BDL
Bi-directional Control for Streams 0-15
BDL 0 STio0 - 15 Operation normal operation: STi0-15 are inputs STio0-15 are outputs bi-directional operation: STi0-15 tied low internally STio0-15 are bi-directional
1
5
RBEREN
PRBS Receiver Enable When this bit is low, all the BER receivers are disabled. To enable any BER receivers, this bit MUST be high. PRBS Transmitter Enable When this bit is low, all the BER transmitters are disabled. To enable any BER transmitters, this bit MUST be high. Block Programming Data These bits refer to the value to be loaded into the connection memory, whenever the memory block programming feature is activated. After the MBPE bit in the Control Register is set to high and the MBPS bit in this register is set to high, the contents of the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3 of the Connection Memory Low and bits 15 - 0 of Connection Memory High are zeroed. Table 18 - Internal Mode Selection Register (IMS) Bits
4
TBEREN
3-1
BPD2 - 0
55
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0001H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 STIO_ PD_EN 7 BDH 6 BDL 5 RBER EN 4 TBER EN 3 BPD 2 2 BPD 1 1
Data Sheet
0 MBPS
BPD 0
Bit 0
Name MBPS
Description Memory Block Programming Start: A zero to one transition of this bit starts the memory block programming function. The MBPS and BPD2 - 0 bits in this register must be defined in the same write operation. Once the MBPE bit in the Control Register is set to high, the device requires two frames to complete the block programming. After the programming function has finished, the MBPS bit returns to low, indicating the operation is completed. When MBPS is high, MBPS or MBPE can be set to low to abort the programming operation. Whenever the microprocessor writes a one to the MBPS bit, the block programming function is started. As long as this bit is high, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting.
Table 18 - Internal Mode Selection Register (IMS) Bits (continued)
External Read/Write Address: 0002H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 SRST SW 0 SRST DPLL
Bit 15 - 2 1
Name Unused SRSTSW
Description Reserved In normal functional mode, these bits MUST be set to zero. Software Reset Bit for Switch When this bit is low, data switching blocks are in normal operation. When this bit is high, data switching blocks are in software reset state. Refer to Table 16, "Address Map for Registers (A13 = 0)" on page 51 for details regarding which registers are affected. Software Reset Bit for DPLL When this bit is low, the DPLL block is in normal operation. When this bit is high, the DPLL block is in software reset state. Refer to Table 16, "Address Map for Registers (A13 = 0)" on page 51 for details regarding which registers are affected. Table 19 - Software Reset Register (SRR) Bits
0
SRSTDPLL
56
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0003H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 FPOF2 EN 7 FPOF1 EN 6 FPOF0 EN 5 CKO5 EN 4 CKO4 EN 3 CKO FPO3 EN 2 CKO FPO2 EN 1 CKO FPO1 EN 0 CKO FPO0 EN
Bit 15 - 9 8
Name Unused FPOF2EN
Description Reserved In normal functional mode, these bits MUST be set to zero. FPo_OFF2/FPo5 Enable When this bit is high, output frame pulse FPo_OFF2/FPo5 is enabled. When this bit is low, output frame pulse FPo_OFF2/FPo5 is in high impedance state. FPo_OFF1 Enable When this bit is high, output frame pulse FPo_OFF1 is enabled. When this bit is low, output frame pulse FPo_OFF1 is in high impedance state. FPo_OFF0 Enable When this bit is high, output frame pulse FPo_OFF0 is enabled. When this bit is low, output frame pulse FPo_OFF0 is in high impedance state. CKo5 Enable When this bit is high, output clock CKo5 is enabled. When this bit is low, output clock CKo5 is in high impedance state. CKo5 is available in Master mode or in Slave mode with SLV_DPLLEN set. CKo4 Enable When this bit is high, output clock CKo4 is enabled. When this bit is low, output clock CKo4 is in high impedance state. CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set. CKo3 and FPo3 Enable When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled. When this bit is low, CKo3 and FPo3 are in high impedance state. CKo2 and FPo2 Enable When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled. When this bit is low, CKo2 and FPo2 are in high impedance state. CKo1 and FPo1 Enable When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled. When this bit is low, CKo1 and FPo1 are in high impedance state. CKo0 and FPo0 Enable When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled. When this bit is low, CKo0 and FPo0 are in high impedance state.
7
FPOF1EN
6
FPOF0EN
5
CKO5EN
4
CKO4EN
3
CKOFPO3 EN CKOFPO2 EN CKOFPO1 EN CKOFPO0 EN
2
1
0
Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
57
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0004H Reset Value: 0000H
15 CKO4 P 14 CKO4 SEL 13 CKO FPO3 SEL1 12 CKO FPO3 SEL0 11 CKO3 P 10 FPO3 P 9 FPO3 POS 8 CKO2 P 7 FPO2 P 6 FPO2 POS 5 CKO1 P 4 FPO1 P 3 FPO1 POS 2 CKO0 P 1 FPO0 P 0 FPO0 POS
Bit 15
Name CKO4P
Description Output Clock (CKo4) Polarity Selection When this bit is low, the output clock CKo4 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo4 rising edge aligns with the frame boundary. CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set. Output Clock (CKo4) Frequency Selection When this bit is low, the output clock CKo4 is 2.048 MHz. When this bit is high, the output clock CKo4 is 1.544 MHz. CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set. Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle Selection
CKOFPO3 SEL1 - 0 00 01 10 11 FPo3 244 ns 122 ns 61 ns 30 ns CKo3 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz
14
CKO4SEL
13 - 12
CKOFPO3 SEL1 - 0
11
CKO3P
Output Clock (CKo3) Polarity Selection When this bit is low, the output clock CKo3 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo3 rising edge aligns with the frame boundary. Output Frame Pulse (FPo3) Polarity Selection When this bit is low, the output frame pulse FPo3 has the negative frame pulse format. When this bit is high, the output frame pulse FPo3 has the positive frame pulse format. Output Frame Pulse (FPo3) Position When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus). Output Clock (CKo2) Polarity Selection When this bit is low, the output clock CKo2 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo2 rising edge aligns with the frame boundary. Output Frame Pulse (FPo2) Polarity Selection When this bit is low, the output frame pulse FPo2 has the negative frame pulse format. When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
10
FPO3P
9
FPO3POS
8
CKO2P
7
FPO2P
Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
58
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0004H Reset Value: 0000H
15 CKO4 P 14 CKO4 SEL 13 CKO FPO3 SEL1 12 CKO FPO3 SEL0 11 CKO3 P 10 FPO3 P 9 FPO3 POS 8 CKO2 P 7 FPO2 P 6 FPO2 POS 5 CKO1 P 4 FPO1 P 3 FPO1 POS 2 CKO0 P
Data Sheet
1 FPO0 P
0 FPO0 POS
Bit 6
Name FPO2POS
Description Output Frame Pulse (FPo2) Position When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus). Output Clock (CKo1) Polarity Selection When this bit is low, the output clock CKo1 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo1 rising edge aligns with the frame boundary. Output Frame Pulse (FPo1) Polarity Selection When this bit is low, the output frame pulse FPo1 has the negative frame pulse format. When this bit is high, the output frame pulse FPo1 has the positive frame pulse format. Output Frame Pulse (FPo1) Position When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus). Output Clock (CKo0) Polarity Selection When this bit is low, the output clock CKo0 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo0 rising edge aligns with the frame boundary. Output Frame Pulse (FPo0) Polarity Selection When this bit is low, the output frame pulse FPo0 has the negative frame pulse format. When this bit is high, the output frame pulse FPo0 has the positive frame pulse format. Output Frame Pulse (FPo0) Position When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).
5
CKO1P
4
FPO1P
3
FPO1POS
2
CKO0P
1
FPO0P
0
FPO0POS
Note: In Divided Slave modes, CKo3 - 1 cannot exceed frequency of CKi. Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set.
Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)
59
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0005H - 0007H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 FP19 EN 9 FOF[n] OFF7 8 FOF[n] OFF6 7 FOF[n] OFF5 6 FOF[n] OFF4 5 FOF[n] OFF3 4 FOF[n] OFF2 3 FOF[n] OFF1 2 FOF[n] OFF0 1 FOF[n] C1 0 FOF[n] C0
Bit 15 - 11 10
Name Unused
FP19EN
Description Reserved. In normal functional mode, these bits MUST be set to zero. 19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only) This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to zero. When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to 19.44 MHz without channel offset. When this bit is low, FPo_OFF2 is output frame pulse with channel offset. FPo_OFF[n] Channel Offset The binary value of these bits refers to the channel offset from original frame boundary. Permitted channel offset values depend on bits 1-0 of this register. FPo_OFF[n] Control bits
FOF[n]C 1-0 00 01 10 11 Data Rate (Mbps) 2.048 4.096 8.192 16.384 FPo_OFF[n] Pulse Cycle Width one 4.096 MHz clock one 8.192 MHz clock one 16.384 MHz clock one 16.384 MHz clock FOF[n]OFF7 - 0 Permitted Channel Offset 0 - 31 0 - 63 0 - 127 0 - 255 Polarity Control FPO0P FPO1P FPO2P FPO2P Position Control FPO0POS FPO1POS FPO2POS FPO2POS
9-2
FOF[n]OFF7 - 0
1-0
FOF[n]C1 - 0
Note: [n] denotes output offset frame pulse from 0 to 2.
Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
60
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read Address: 0010H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 OUT ERR 0 IN ERR
Bit 15 - 2 1
Name Unused OUTERR
Description Reserved In normal functional mode, these bits are zero. Output Error (Read Only) This bit is set high when the total number of output channels is programmed to be more than the maximum capacity of 4096, in which case the output channels beyond the maximum capacity should be disabled. This bit will be cleared automatically after programming is corrected. Input Error (Read Only) This bit is set high when the total number of input channels is programmed to be more than the maximum capacity of 4096, in which case the input channels beyond the maximum capacity should be disabled.This bit will be cleared automatically after programming is corrected. Table 23 - Internal Flag Register (IFR) Bits - Read Only
0
INERR
External Read Address: 00011H Reset Value: 0000H
15 BER F15 14 BER F14 13 BER F13 12 BER F12 11 BER F11 10 BER F10 9 BER F9 8 BER F8 7 BER F7 6 BER F6 5 BER F5 4 BER F4 3 BER F3 2 BER F2 1 BER F1 0 BER F0
Bit 15 - 0
Name BERF[n]
Description BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 0 - 15.
Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only
61
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 00012H Reset Value: 0000H
15 BER F31 14 BER F30 13 BER F29 12 BER F28 11 BER F27 10 BER F26 9 BER F25 8 BER F24 7 BER F23 6 BER F22 5 BER F21 4 BER F20 3 BER F19 2 BER F18 1 BER F17 0 BER F16
Bit 15 - 0
Name BERF[n]
Description BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 16 - 31.
Table 25 - BER Error Flag Register 1 (BERFR1) Bits - Read Only
External Read Address: 00013H Reset Value: 0000H
15 BER L15 14 BER L14 13 BER L13 12 BER L12 11 BER L11 10 BER L10 9 BER L9 8 BER L8 7 BER L7 6 BER L6 5 BER L5 4 BER L4 3 BER L3 2 BER L2 1 BER L1 0 BER L0
Bit 15 - 0
Name BERL[n]
Description BER Receiver Lock[n] If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 0 - 15.
Table 26 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
62
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read Address: 00014H Reset Value: 0000H
15 BER L31 14 BER L30 13 BER L29 12 BER L28 11 BER L27 10 BER L26 9 BER L25 8 BER L24 7 BER L23 6 BER L22 5 BER L21 4 BER L20 3 BER L19 2 BER L18 1 BER L17 0 BER L16
Bit 15 - 0
Name BERL[n]
Description BER Receiver Lock[n]: If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 16 - 31.
Table 27 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
External Read/Write Address: 0040H Reset Value: 0000H 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ST4_ LIM
4
0
3
0
2
0
1
RFRE
0
DPLL _IRM
Bit 15-6 5
Name Unused ST4_LIM
Description Reserved In normal functional mode, these bits MUST be set to zero. Stratum 4E Limits Select Bit When this bit is high, the Stratum 4E limits are used for reference monitoring (i.e. +/-64.713 ppm and +/-82.487 ppm over 10 seconds).When this bit is low, more relaxed Relaxed Stratum 4E limits are used for reference monitoring (i.e. +/-240 ppm and +/-250 ppm over 10 seconds). This is used in applications where a low quality clock (+/-100 ppm) is used as a reference. Reserved In normal functional mode, these bits MUST be set to zero. Reference Frequency Register Enable When this bit is low, the reference frequency value used in the DPLL comes from appropriate reference frequency detector. When this bit is high, the reference frequency value comes from Reference Frequency Register (RFR). DPLL Internal Reset Mode When this bit is low, the DPLL module is in the operational state. When this bit is high, the DPLL module is in the power saving mode. Registers are not reset and are still accessible in the power saving mode. Table 28 - DPLL Control Register (DPLLCR) Bits
4-2 1
Unused RFRE
0
DPLL_ IRM
63
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0041H Reset Value: 0000H 15
0
14
0
13
0
12
0
11
R3F2
10
R3F1
9
R3F0
8
R2F2
7
R2F1
6
R2F0
5
R1F2
4
R1F1
3
R1F0
2
R0F2
1
R0F1
0
R0F0
Bit 15-12 11 - 9
Name Unused R3F2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Reference 3 Frequency Bits When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF3 input frequency. When the RFRE bit is low, these bits are ignored.
R3F2 0 0 0 0 1 1 1 1 R3F1 0 0 1 1 0 0 1 1 R3F0 0 1 0 1 0 1 0 1 REF 3 Input Frequency 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
8-6
R2F2 - 0
Reference 2 Frequency Bits: When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF2 input frequency. When the RFRE bit is low, these bits are ignored.
R2F2 0 0 0 0 1 1 1 1 R2F1 0 0 1 1 0 0 1 1 R2F0 0 1 0 1 0 1 0 1 REF 2 Input Frequency 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
Table 29 - Reference Frequency Register (RFR) Bits
64
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0041H Reset Value: 0000H 15
0
Data Sheet
14
0
13
0
12
0
11
R3F2
10
R3F1
9
R3F0
8
R2F2
7
R2F1
6
R2F0
5
R1F2
4
R1F1
3
R1F0
2
R0F2
1
R0F1
0
R0F0
Bit 5-3
Name R1F2 - 0
Description Reference 1 Frequency Bits When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF1 input frequency. When the RFRE bit is low, these bits are ignored.
R1F2 0 0 0 0 1 1 1 1 R1F1 0 0 1 1 0 0 1 1 R1F0 0 1 0 1 0 1 0 1 REF 1 Input Frequency 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
2-0
R0F2 - 0
Reference 0 Frequency Bits When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF0 input frequency. When the RFRE bit is low, these bits are ignored.
R0F2 0 0 0 0 1 1 1 1 R0F1 0 0 1 1 0 0 1 1 R0F0 0 1 0 1 0 1 0 1 REF 0 Input Frequency 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
Table 29 - Reference Frequency Register (RFR) Bits (continued)
65
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0042H Reset Value: 16B1H 15
CFN 15
14
CFN 14
13
CFN 13
12
CFN 12
11
CFN 11
10
CFN 10
9
CFN 9
8
CFN 8
7
CFN 7
6
CFN 6
5
CFN 5
4
CFN 4
3
CFN 3
2
CFN 2
1
CFN 1
0
CFN 0
Bit 15 - 0
Name CFN15 - 0
Description Center Frequency Number (CFN) Lower 16 Bits: The total binary value of these bits and the CFRU register bits defines the output center frequency number according to the following formula:
CFN fOUT = ----------- x fMCLK 26 2
where, fOUT is desired output center frequency, while fMCLK is frequency of DPLL master clock. For given master clock frequency of 100 MHz, and desired output center frequency of 65.536 MHz, the CFN has the value of:
CFN = 2
26 26 65.536MHz x ------------------------------ = 2 x 0.65536 = 43980465 = 29F16B1H 100MHz
The register contents should be changed only if compensation for input oscillator (or crystal) frequency offset is required. e.g., if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i of 20.0004 MHz), the CFN should be programmed to be:
CFN = 2
26 26 65.536MHz x ---------------------------------- = 2 x 0.65534689 = 43979585 = 29F1341H 100.002MHz
The default value of this register SHOULD NOT be changed in any other circumstances. Table 30 - Centre Frequency Register - Lower 16 Bits (CFRL)
External Read/Write Address: 0043H Reset Value: 029FH 15
0
14
0
13
0
12
0
11
0
10
0
9
CFN 25
8
CFN 24
7
CFN 23
6
CFN 22
5
CFN 21
4
CFN 20
3
CFN 19
2
CFN 18
1
CFN 17
0
CFN 16
Bit 15 - 10 9-0
Name Unused CFN25 - 16
Description Reserved. In normal functional mode, these bits MUST be set to zero. Center Frequency Number (CFN) Upper 10 Bits: The total binary value of these bits and the CFRL register bits represents the center frequency number (CFN) explained under CFRL register bits explanation. The default value of this register should be changed only if compensation for input oscillator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other circumstances. Table 31 - Centre Frequency Register - Upper 10 Bits (CFRU)
66
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read Only Address: 0045H 15
0
14
FOF 14
13
FOF 13
12
FOF 12
11
FOF 11
10
FOF 10
9
FOF 9
8
FOF 8
7
FOF 7
6
FOF 6
5
FOF 5
4
FOF 4
3
FOF 3
2
FOF 2
1
FOF 1
0
FOF 0
Bit 15 14 - 0
Name Unused FOF14 - 0
Description Reserved. In normal functional mode, this bit is zero. Frequency Offset Bits: The binary value of these bits represents the current deviation of the DPLL output from its center frequency. Defined in same units as CFN in the 2's complement format.
Note 1:
Output frequency offset, relative to master clock, will be represented as the following: +10 ppm: CFN x 0.00001 = 440 = 01B8H -10 ppm: CFN x (-0.00001) = -440 = 7E48H
Table 32 - Frequency Offset Register (FOR) Bits - Read Only
External Read/Write Address: 0047H Reset Value: 000FH 15
LDT 15
14
LDT 14
13
LDT 13
12
LDT 12
11
LDT 11
10
LDT 10
9
LDT 9
8
LDT 8
7
LDT 7
6
LDT 6
5
LDT 5
4
LDT 4
3
LDT 3
2
LDT 2
1
LDT 1
0
LDT 0
Bit 15 - 0
Name LDT15 - 0
Description Lock Detect Threshold Bits The binary value of these bits defines the upper limit of the absolute phase from the phase detector output for lock detection. When the value of the absolute phase is less than or equal to LDT for duration of time defined by the LDIR register, the DPLL locks. When the value of the absolute phase is greater than LDT for duration of time defined by the LDIR register divided by 256, the DPLL does not lock.
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference using the following formula: LDT = MAX_EXP_JITTER (ns) x 2 15.2 (ns) Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns) (assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2) x 2 = 642 = 0282H Table 33 - Lock Detector Threshold Register (LDTR) Bits
67
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0048H Reset Value: 2C00H 15
LDI 15
14
LDI 14
13
LDI 13
12
LDI 12
11
LDI 11
10
LDI 10
9
LDI 9
8
LDI 8
7
LDI 7
6
LDI 6
5
LDI 5
4
LDI 4
3
LDI 3
2
LDI 2
1
LDI 1
0
LDI 0
Bit 15 - 0
Name LDI15 - 0
Description Lock Detector Interval Bits The binary value of these bits defines the time interval that the output phase detector must be below the lock detect threshold to declare lock. Unsigned representation of the LDI bits is defined in 4 ms intervals. Table 34 - Lock Detector Interval Register (LDIR) Bits
External Read/Write Address: 0049H Reset Value: 099FH (see Note) 15
0
14
0
13
0
12
SRL 12
11
SRL 11
10
SRL 10
9
SRL 9
8
SRL 8
7
SRL 7
6
SRL 6
5
SRL 5
4
SRL 4
3
SRL 3
2
SRL 2
1
SRL 1
0
SRL 0
Bit 15 - 13 12 - 0
Name Unused SRL12 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Slew Rate Limit Bits The binary value of these bits defines the maximum rate of DPLL phase change (phase slope), where the phase represents difference between the input reference and output feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is 56 ppm ('h099F/CFN = 56 ppm).
Table 35 - Slew Rate Limit Register (SRLR) Bits
68
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 004BH Reset Value: 0000H 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
MTR
6
PRS 1
5
PRS 0
4
PMS 2
3
PMS 1
2
PMS 0
1
FDM 1
0
FDM 0
Bit 15 - 8 7
Name Unused MTR
Description Reserved In normal functional mode, these bits MUST be set to zero. MTIE Reset When this bit is low, the MTIE circuit applies a phase offset between the reference input clock and the DPLL output clock and the phase offset value is maintained. When this bit is high, MTIE circuit is in its reset state and the phase offset value is reset to zero, causing alignment of the DPLL output clocks to nearest edge of the selected input reference. Preferred Reference Selection Bits These bits select the preferred reference from one of the input references. They are used only if the PMS2-0 bits are set to 001. Otherwise, these bits are ignored.
PRS1 0 0 1 1 PRS0 0 1 0 1 Preferred Reference Selection REF0 REF1 REF2 REF3
6-5
PRS1 - 0
4-2
PMS2 - 0
Preference Mode Selection Bits These bits select one of the preference modes:
PMS2 0 0 0 0 1 1 PMS1 0 0 1 1 0 0 110 - 111 PMS0 0 1 0 1 0 1 Preference Mode No Preference Preference as per the setting of the PRS1 - 0 bits Force REF0 Force REF1 Force REF2 Force REF3 Reserved
If in automatic mode with a preferred reference (PMS2-0 = 001 and FDM1-0 = 00), the automatic state machine will only switch between two references (as per Table 8). Please see Section12.1.3.2, "Automatic Reference Switching With Preferences" on page 41 for more details. Table 36 - Reference Change Control Register (RCCR) Bits
69
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 004BH Reset Value: 0000H 15
0
Data Sheet
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
MTR
6
PRS 1
5
PRS 0
4
PMS 2
3
PMS 1
2
PMS 0
1
FDM 1
0
FDM 0
Bit 1-0
Name FDM1 - 0
Description Force DPLL Timing Mode These bits force the DPLL into one of the valid operation modes.
FDM1 0 0 1 1 FDM0 0 1 0 1 DPLL TIMING Mode Automatic Normal Holdover Freerun
Table 36 - Reference Change Control Register (RCCR) Bits (continued)
External Read Only Address: 004CH 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
SLM
7
LST
6
RFR2
5
RFR1
4
RFR0
3
RES1
2
RES0
1
DPM1
0
DPM0
Bit 15 - 9 8
Name Unused SLM
Description Reserved In normal functional mode, these bits are zero. Slew Rate Limiter Status Bit If the device sets this bit to high, the DPLL phase difference between the input and output clocks is changing at the slew rate limit defined in the Slew Rate Limit Register (SRLR). Lock Status Bit If the device sets this bit to high, while the LDTR and LDIR registers are programmed properly, the DPLL output clocks are locked to the selected input reference. If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
7
LST
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only
70
Zarlink Semiconductor Inc.
ZL50022
External Read Only Address: 004CH 15
0
Data Sheet
14
0
13
0
12
0
11
0
10
0
9
0
8
SLM
7
LST
6
RFR2
5
RFR1
4
RFR0
3
RES1
2
RES0
1
DPM1
0
DPM0
Bit 6-4
Name RFR2 - 0
Description Reference Frequency Indicator Bits These bits represent the frequency of the selected reference indicated by the reference bits (RES1 - 0) in this register.
RFR2 0 0 0 0 1 1 1 1 RFR1 0 0 1 1 0 0 1 1 RFR0 0 1 0 1 0 1 0 1 Frequency of the Selected Reference 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44MHz Reserved
3-2
RES1 - 0
Reference Select Indicator Bits: These bits indicate which one of the four reference inputs (REF0 - 3 pins) is being selected by the device.
RES1 0 0 1 1 RES0 0 1 0 1 Input Reference in use REF 0 REF 1 REF 2 REF 3
1-0
DPM1 - 0
DPLL Timing Mode Status Bits: These bits indicate the DPLL's timing mode status.
DPM1 0 0 1 1 DPM0 0 1 0 1 DPLL Timing Mode State MTIE Normal Holdover Freerun
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only (continued)
71
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read Only Address: 0066H 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
LCI
2
RCI
1
HOI
0
0
Bit 15 - 4 3 2 1
Name Unused LCI RCI HOI
Description Reserved In normal functional mode, these bits is zero. Lock Change Interrupt Bit If the device sets this bit to high, the device lock status has changed. Reference Change Interrupt Bit If the device sets this bit to high, the selected reference has changed. Holdover Interrupt Bit If the device sets this bit to high, the device has entered or recovered from the holdover/MTIE mode. Reserved In normal functional mode, this bit is zero.
0
Note 1: Note 2:
Unused
If any of these bits are set, the interrupt output will become active unless the Interrupt Mask Register (IMR) has a high value for that particular bit. Any of these bits can be cleared by setting the appropriate bit in the Interrupt Clear Register.
Table 38 - Interrupt Register (IR) Bits - Read Only
External Read/Write Address: 0067H Reset Value: 000FH 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
LIM
2
RIM
1
HIM
0
1
Bit 15 - 4 3 2 1
Name Unused LIM RIM HIM
Description Reserved In normal functional mode, these bits MUST be set to zero. Lock Interrupt Mask Bit When this bit is high, it masks the lock status change interrupt. Reference Change Interrupt Mask Bit When this bit is high, it masks the reference change interrupt. Holdover Interrupt Mask Bit When this bit is high, it masks the holdover entry/exit interrupt. Table 39 - Interrupt Mask Register (IMR) Bits
72
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0067H Reset Value: 000FH 15
0
Data Sheet
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
LIM
2
RIM
1
HIM
0
1
Bit 0
Name Unused
Description Reserved In normal functional mode, this bit MUST be set to one. Table 39 - Interrupt Mask Register (IMR) Bits (continued)
External Read/Write Address: 0068H Reset Value: 0000H 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
ICB 3
2
ICB 2
1
ICB 1
0
1
Bit 15 - 4 3-1
Name Unused ICB3 - 1
Description Reserved In normal functional mode, these bits MUST be set to zero. Interrupt Clear Bits Writing a "1" to any bit in this register will clear the corresponding bit in the Interrupt Register (IR). The Interrupt Clear Register is self-clearing, i.e. once it has completed its action, the ICR register bit returns to 0. Reserved In normal functional mode, this bit MUST be set to one. Table 40 - Interrupt Clear Register (ICR) Bits
0
Unused
73
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read Only Address: 0069H 15
R3 FML
14
R3 FMU
13
R3 FL
12
R3 FU
11
R2 FML
10
R2 FMU
9
R2 FL
8
R2 FU
7
R1 FML
6
R1 FMU
5
R1 FL
4
R1 FU
3
R0 FML
2
R0 FMU
1
R0 FL
0
R0 FU
Bit 15
Name R3FML
Description Reference 3 Multi-period Lower Limit Fail Bit f the device sets this bit to high, the input REF3 fails the multi-period lower limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 3 Multi-period Upper Limit Fail Bit If the device sets this bit to high, the input REF3 fails the multi-period upper limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 3 Single Period Lower Limit Fail Bit If the device sets this bit to high, the input REF3 fails the single-period lower limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 3 Single Period Upper Limit Fail Bit If the device sets this bit to high, the input REF3 fails the single-period upper limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 2 Multi-period Lower Limit Fail Bit If the device sets this bit to high, the input REF2 fails the multi-period lower limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 2 Multi-period Upper Limit Fail Bit If the device sets this bit to high, the input REF2 fails the multi-period upper limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 2 Single Period Lower Limit Fail Bit If the device sets this bit to high, the input REF2 fails the single-period lower limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 2 Single Period Upper Limit Fail Bit If the device sets this bit to high, the input REF2 fails the single-period upper limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 1 Multi-period Lower Limit Fail Bit If the device sets this bit to high, the input REF1 fails the multi-period lower limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 1 Multi-period Upper Limit Fail Bit If the device sets this bit to high, the input REF1 fails the multi-period upper limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 1 Single Period Lower Limit Fail Bit If the device sets this bit to high, the input REF1 fails the single-period lower limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 1 Single Period Upper Limit Fail Bit If the device sets this bit to high, the input REF1 fails the single-period upper limit check. (See Table 11, "Values for Single Period Limits" on page 45)
14
R3FMU
13
R3FL
12
R3FU
11
R2FML
10
R2FMU
9
R2FL
8
R2FU
7
R1FML
6
R1FMU
5
R1FL
4
R1FU
Table 41 - Reference Failure Status Register (RSR) Bits - Read Only
74
Zarlink Semiconductor Inc.
ZL50022
External Read Only Address: 0069H 15
R3 FML
Data Sheet
14
R3 FMU
13
R3 FL
12
R3 FU
11
R2 FML
10
R2 FMU
9
R2 FL
8
R2 FU
7
R1 FML
6
R1 FMU
5
R1 FL
4
R1 FU
3
R0 FML
2
R0 FMU
1
R0 FL
0
R0 FU
Bit 3
Name R0FML
Description Reference 0 Multi-period Lower Limit Fail Bit If the device sets this bit to high, the input REF0 fails the multi-period lower limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 0 Multi-period Upper Limit Fail Bit If the device sets this bit to high, the input REF0 fails the multi-period upper limit check. (See Table 12, "Multi-period Hysteresis Limits" on page 46) Reference 0 Single Period Lower Limit Fail Bit If the device sets this bit to high, the input REF0 fails the single-period lower limit check. (See Table 11, "Values for Single Period Limits" on page 45) Reference 0 Single Period Upper Limit Fail Bit If the device sets this bit to high, the input REF0 fails the single-period upper limit check. (See Table 11, "Values for Single Period Limits" on page 45)
2
R0FMU
1
R0FL
0
R0FU
Table 41 - Reference Failure Status Register (RSR) Bits - Read Only (continued)
External Read/Write Address: 006AH Reset Value: 0000H 15
R3 MML
14
R3 MMU
13
R3 ML
12
R3 MU
11
R2 MML
10
R2 MMU
9
R2 ML
8
R2 MU
7
R1 MML
6
R1 MMU
5
R1 ML
4
R1 MU
3
R0 MML
2
R0 MMU
1
R0 ML
0
R0 MU
Bit 15
Name R3MML
Description Reference 3 Multi-period Lower Limit Mask Bit When this bit is high, it masks the multi-period lower limit check (or forces pass) for REF3. Reference 3 Multi-period Upper Limit Mask Bit When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF3. Reference 3 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF3. Reference 3 Single-period Upper Limit Mask Bit When this bit is high, it masks the single-period upper limit check (or forces pass) for REF3. Table 42 - Reference Mask Register (RMR) Bits
14
R3MMU
13
R3ML
12
R3MU
75
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 006AH Reset Value: 0000H 15
R3 MML
Data Sheet
14
R3 MMU
13
R3 ML
12
R3 MU
11
R2 MML
10
R2 MMU
9
R2 ML
8
R2 MU
7
R1 MML
6
R1 MMU
5
R1 ML
4
R1 MU
3
R0 MML
2
R0 MMU
1
R0 ML
0
R0 MU
Bit 11
Name R2MML
Description Reference 2 Multi-period Lower Limit Mask Bit When this bit is high, it masks the multi-period lower limit check (or forces pass) for REF2. Reference 2 Multi-period Upper Limit Mask Bit When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF2. Reference 2 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF2. Reference 2 Single-period Upper Limit Mask Bit When this bit is high, it masks the single-period upper limit check (or forces pass) for REF2. Reference 1 Multi-period Lower Limit Mask Bit When this bit is high, it masks the multi-period lower limit check (or forces pass) for REF1. Reference 1 Multi-period Upper Limit Mask Bit When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF1. Reference 1 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF1. Reference 1 Single-period Upper Limit Mask Bit When this bit is high, it masks the single-period upper limit check (or forces pass) for REF1. Reference 0 Multi-period Lower Limit Mask Bit When this bit is high, it masks the multi-period lower limit check (or forces pass) for REF0. Reference 0 Multi-period Upper Limit Mask Bit When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF0. Reference 0 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF0. Table 42 - Reference Mask Register (RMR) Bits (continued)
10
R2MMU
9
R2ML
8
R2MU
7
R1MML
6
R1MMU
5
R1ML
4
R1MU
3
R0MML
2
R0MMU
1
R0ML
76
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 006AH Reset Value: 0000H 15
R3 MML
Data Sheet
14
R3 MMU
13
R3 ML
12
R3 MU
11
R2 MML
10
R2 MMU
9
R2 ML
8
R2 MU
7
R1 MML
6
R1 MMU
5
R1 ML
4
R1 MU
3
R0 MML
2
R0 MMU
1
R0 ML
0
R0 MU
Bit 0
Name R0MU
Description Reference 0 Single-period Upper Limit Mask Bit When this bit is high, it masks the single-period upper limit check (or forces pass) for REF0. Table 42 - Reference Mask Register (RMR) Bits (continued)
External Read Only Address: 006BH 15
0
14
0
13
0
12
0
11
R3FS 2
10
R3FS 1
9
R3FS 0
8
R2FS 2
7
R2FS 1
6
R2FS 0
5
R1FS 2
4
R1FS 1
3
R1FS 0
2
R0FS 2
1
R0FS 1
0
R0FS 0
Bit 15 - 12 11 - 9
Name Unused R3FS2 - 0
Description Reserved. In normal functional mode, these bits are zero. Reference 3 Frequency Status Bits These bits report detected frequency of REF3.
R3FS2 0 0 0 0 1 1 1 1 R3FS1 0 0 1 1 0 0 1 1 R3FS0 0 1 0 1 0 1 0 1 REF3 Frequency Measurement 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
Table 43 - Reference Frequency Status Register (RFSR) Bits - Read only
77
Zarlink Semiconductor Inc.
ZL50022
External Read Only Address: 006BH 15
0
Data Sheet
14
0
13
0
12
0
11
R3FS 2
10
R3FS 1
9
R3FS 0
8
R2FS 2
7
R2FS 1
6
R2FS 0
5
R1FS 2
4
R1FS 1
3
R1FS 0
2
R0FS 2
1
R0FS 1
0
R0FS 0
Bit 8-6
Name R2FS2 - 0
Description Reference 2 Frequency Status Bits: These bits report detected frequency of REF2.
R2FS2 0 0 0 0 1 1 1 1 R2FS1 0 0 1 1 0 0 1 1 R2FS0 0 1 0 1 0 1 0 1 REF 2 Frequency Measurement 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
5-3
R1FS2 - 0
Reference 1 Frequency Status Bits: These bits report detected frequency of REF1.
R1FS2 0 0 0 0 1 1 1 1 R1FS1 0 0 1 1 0 0 1 1 R1FS0 0 1 0 1 0 1 0 1 REF1 Frequency Measurement 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
2-0
R0FS2 - 0
Reference 0 Frequency Status Bits: These bits report detected frequency of REF0.
R0FS2 0 0 0 0 1 1 1 1 R0FS1 0 0 1 1 0 0 1 1 R0FS0 0 1 0 1 0 1 0 1 REF0 Frequency Measurement 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved
Table 43 - Reference Frequency Status Register (RFSR) Bits - Read only (continued)
78
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 006CH Reset Value: 0002H 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
OJP2
1
OJP1
0
OJP0
Bit 15 - 3 2-0
Name Unused OJP2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Output Jitter Performance Bits These bits are used to control the DPLL output jitter performance with respect to the noise received through the output pins. The higher value (unsigned) means more filtering, while zero means filter bypass. The default value of 2H gives the best performance for most circumstances. Table 44 - Output Jitter Control Register (OJCR) Bits
External Read/Write Address: 0100H - 011FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
STIN[n] DR3
STIN[n] DR2
STIN[n] DR1
STIN[n] DR0
Bit
15 - 9 8-6
Name Unused STIN[n]BD2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Input Stream[n] Bit Delay Bits. The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits
Sampling Point (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 3/4 point 1/4 point 2/4 point 4/4 point 4/4 point Sampling Point (16.384 Mbps streams) 2/4 point
5-4
STIN[n]SMP1 - 0
STIN[n]SMP1-0 00 01 10 11
Table 45 - Stream Input Control Register 0 - 31 (SICR0 - 31) BIts
79
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0100H - 011FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Data Sheet
0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
STIN[n] DR3
STIN[n] DR2
STIN[n] DR1
STIN[n] DR0
Bit 3-0
Name STIN[n]DR3 - 0 Input Data Rate Selection Bits:
STIN[n]DR3-0 0000 0001 0010 0011 0100 0101 - 1111
Description
Data Rate Stream Unused 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Reserved
Note: [n] denotes input stream from 0 - 31.
Table 45 - Stream Input Control Register 0 - 31 (SICR0 - 31) BIts (continued)
80
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0120H - 013FH Reset Value: 0000H
15 14 13 12 11 STIN[n] Q3C2 10 STIN[n] Q3C1 9 STIN[n] Q3C0 8 STIN[n] Q2C2 7 STIN[n] Q2C1 6 STIN[n] Q2C0 5 STIN[n] Q1C2 4 STIN[n] Q1C1 3 STIN[n] Q1C0 2 STIN[n] Q0C2 1 STIN[n] Q0C1 0 STIN[n] Q0C0
0
0
0
0
Bit 15 - 12 11 - 9
Name Unused STIN[n]Q3C2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Quadrant Frame 3 Control Bits These three bits are used to control STi[n]'s quadrant frame 3, which is defined as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q3C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
8-6
STIN[n]Q2C2 - 0
Quadrant Frame 2 Control Bits These three bits are used to control STi[n]'s quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q2C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
81
Zarlink Semiconductor Inc.
ZL50022
External Read/Write Address: 0120H - 013FH Reset Value: 0000H
15 14 13 12 11 STIN[n] Q3C2 10 STIN[n] Q3C1 9 STIN[n] Q3C0 8 STIN[n] Q2C2 7 STIN[n] Q2C1 6 STIN[n] Q2C0 5 STIN[n] Q1C2 4 STIN[n] Q1C1 3 STIN[n] Q1C0 2 STIN[n] Q0C2 1
Data Sheet
0 STIN[n] Q0C0
0
0
0
0
STIN[n] Q0C1
Bit 5-3
Name STIN[n]Q1C2 - 0
Description Quadrant Frame 1 Control Bits These three bits are used to control STi[n]'s quadrant frame 1, which is defined as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q1C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
2-0
STIN[n]Q0C2 - 0
Quadrant Frame 0 Control Bits These three bits are used to control STi[n]'s quadrant frame 0, which is defined as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
Note: [n] denotes input stream from 0 - 31.
Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits (continued)
82
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0200H - 021FH Reset Value: 0000H
15 14 13 12 11 STOHZ [n]A2 10 STOHZ [n]A1 9 STOHZ [n]A0 8 STO[n] FA1 7 STO[n] FA0 6 STO[n] AD2 5 STO[n] AD1 4 STO[n] AD0 3 STO[n] DR3 2 STO[n] DR2 1 STO[n] DR1 0 STO[n] DR0
0
0
0
0
Bit 15 - 12 11 - 9
Name Unused STOHZ[n]A2 - 0
(Valid only for STio0-15)
Description Reserved In normal functional mode, these bits MUST be set to zero. STOHZ Additional Advancement Bits
STOHZ[n]A2-0 000 001 010 011 100 101-111 Additional Advancement (2.048 Mbps, 4.096 Mbps, 8.192 Mbps) 0 bit 1/4 bit 2/4 bit 3/4 bit 4/4 bit Reserved Additional Advancement (16.384 Mbps streams) 0 bit 2/4 bit 4/4 bit Reserved
8-7
STO[n]FA1 - 0
Output Stream[n] Fractional Advancement Bits
STO[n]FA1-0 00 01 10 11 Advancement (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 0 1/4 bit 2/4 bit 3/4 bit Advancement (16.384 Mbps streams) 0 2/4 Reserved
6-4
STO[n]AD2 - 0
Output Stream[n] Bit Advancement Selection Bits The binary value of these bits refers to the number of bits that the output stream is to be advanced relative to FPo. The maximum value is 7. Zero means no advancement. Output Data Rate Selection Bits
STIN[n]DR3 - 0 0000 0001 0010 0011 0100 0101 - 1111 Data Rate disabled: STio HiZ (STOHZ driven high) 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Reserved
3-0
STO[n]DR3 - 0
Note: [n] denotes output stream from 0 - 31.
Table 47 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits
83
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0300H - 031FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 ST[n] BRS7 6 ST[n] BRS6 5 ST[n] BRS5 4 ST[n] BRS4 3 ST[n] BRS3 2 ST[n] BRS2 1 ST[n] BRS1 0 ST[n] BRS0
Bit 15 - 8 7-0
Name Unused ST[n] BRS7 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] BER Receive Start Bits The binary value of these bits refers to the input channel in which the BER data starts to be compared.
Note: [n] denotes input stream from 0 - 31.
Table 48 - BER Receiver Start Register [n] (BRSR[n]) Bits
External Read/Write Address: 0320H - 033FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 ST[n] BL8 7 ST[n] BL7 6 ST[n] BL6 5 ST[n] BL5 4 ST[n] BL4 3 ST[n] BL3 2 ST[n] BL2 1 ST[n] BL1 0 ST[n] BL0
Bit 15 - 9 8-0
Name Unused ST[n] BL8 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] BER Length Bits The binary value of these bits refers to the number of consecutive channels expected to receive the BER pattern. The maximum number of BER channels is 32, 64, 128 and 256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels is 1. If these bits are set to zero, no BER test will be performed.
Note: [n] denotes input stream from 0 - 31.
Table 49 - BER Receiver Length Register [n] (BRLR[n]) Bits
84
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
External Read/Write Address: 0340H - 035FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 ST[n] CBER 0 ST[n] SBER
Bit 15 - 2 1
Name Unused ST[n] CBER ST[n] SBER
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] Bit Error Rate Counter Clear When this bit is high, it resets the internal bit error counter and the stream BER Receiver Error Register to zero. Stream[n] Bit Error Rate Test Start When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set in the IMS Register first.
0
Note: [n] denotes input stream from 0 - 31.
Table 50 - BER Receiver Control Register [n] (BRCR[n]) Bits
External Read Address: 0360H - 037FH Reset Value: 0000H
15 ST[n] BC15 14 ST[n] BC14 13 ST[n] BC13 12 ST[n] BC12 11 ST[n] BC11 10 ST[n] BC10 9 ST[n] BC9 8 ST[n] BC8 7 ST[n] BC7 6 ST[n] BC6 5 ST[n] BC5 4 ST[n] BC4 3 ST[n] BC3 2 ST[n] BC2 1 ST[n] BC1 0 ST[n] BC0
Bit 15 - 0
Name ST[n] BC15 - 0
Description Stream[n] BER Count Bits (Read Only) The binary value of these bits refers to the bit error counts. When it reaches its maximum value of 0xFFFF, the value will be held and will not rollover.
Note: [n] denotes input stream from 0 - 31.
Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
85
Zarlink Semiconductor Inc.
ZL50022
24.0
24.1
Data Sheet
Memory
Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB (Note 1) Stream Address (St0 - 31) A12 0 0 0 0 0 0 0 0 0 . . . . . 0 0 . . . . . . 1 1 A11 0 0 0 0 0 0 0 0 1 . . . . . 1 1 . . . . . . 1 1 A10 0 0 0 0 1 1 1 1 0 . . . . . 1 1 . . . . . . 1 1 A9 0 0 1 1 0 0 1 1 0 . . . . . 1 1 . . . . . . 1 1 A8 0 1 0 1 0 1 0 1 0 . . . . . 0 1 . . . . . . 0 1 Stream [n] Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 . . . . . Stream 14 Stream 15 . . . . . . Stream 30 Stream 31 A7 0 0 . . 0 0 0 0 . . 0 0 . . . . 0 0 . . . . 1 1 A6 0 0 . . 0 0 0 0 . . 0 0 . . . . 1 1 . . . . 1 1 A5 0 0 . . 0 0 1 1 . . 1 1 . . . . 1 1 . . . . 1 1 A4 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 Channel Address (Ch0 - 255) A3 0 0 . . 1 1 0 0 . . 1 1 . . . . 1 1 . . . . 1 1 A2 0 0 . . 1 1 0 0 . 1 1 . . . . 1 1 . . . . 1 1 A1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 A0 0 1 . . 0 1 0 1 . . 0 1 . . . . 0 1 . . . . 0 1 Channel [n] Ch 0 Ch 1 . . Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 . . Ch 62 Ch 63 (Note 3) . . . . Ch126 Ch 127 (Note 4) . . . . Ch 254 Ch 255 (Note 5)
A13
1 1 1 1 1 1 1 1 1 . . . . . 1 1 . . . . . . 1 1
Note 1: Note Note Note Note 2: 3: 4: 5:
A13 must registers. Channels Channels Channels Channels
be high for access to data and connection memory positions. A13 must be low to access internal 0 0 0 0 to to to to 31 are used when serial stream is at 2.048 Mbps. 63 are used when serial stream is at 4.096 Mbps. 127 are used when serial stream is at 8.192 Mbps. 255 are used when serial stream is at 16.384 Mbps.
Table 52 - Address Map for Memory Locations (A13 = 1)
86
Zarlink Semiconductor Inc.
ZL50022
24.2 Connection Memory Low (CM_L) Bit Assignment
Data Sheet
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in Table 53 on page 87.
15
UA EN
14
V/C
13
SSA 4
12
SSA 3
11
SSA 2
10
SSA 1
9
SSA 0
8
SCA 7
7
SCA 6
6
SCA 5
5
SCA 4
4
SCA 3
3
SCA 2
2
SCA 1
1
SCA 0
0
CMM =0
Bit 15
Name UAEN
Description Conversion between -law and A-law Enable When this bit is low, normal switch without -law/A-law conversion. Connection memory high will be ignored. When this bit is high, switch with -law/A-law conversion, and connection memory high controls the conversion method. Variable/Constant Delay Control When this bit is low, the output data for this channel will be taken from constant delay memory. When this bit is set to high, the output data for this channel will be taken from variable delay memory. Note that VAREN must be set in Control Register first. Source Stream Address The binary value of these 5 bits represents the input stream number. Source Channel Address The binary value of these 8 bits represents the input channel number. Connection Memory Mode = 0 If this is low, the connection memory is in the normal switching mode. Bit 13 1 are the source stream number and channel number.
14
V/C
13 - 9 8-1 0
SSA4 - 0 SCA7 - 0 CMM = 0
Note: For proper
-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
87
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode as shown in Table 54 on page 88.
15
UA EN
14
0
13
0
12
0
11
0
10
MSG 7
9
MSG 6
8
MSG 5
7
MSG 4
6
MSG 3
5
MSG 2
4
MSG 1
3
MSG 0
2
PCC 1
1
PCC 0
0
CMM =1
Bit 15
Name UAEN
Description Conversion between -law and A-law Enable (Message mode only) When this bit is low, message mode has no -law/A-law conversion. Connection memory high will be ignored. When this bit is high, message mode has -law/A-law conversion, and connection memory high controls the conversion method. Reserved In normal functional mode, these bits MUST be set to zero. Message Data Bits 8-bit data for the message mode. Not used in the per-channel tristate and BER test modes. Per-Channel Control Bits These two bits control the corresponding entry's value on the STio stream.
PC C1 0 0 1 1 PC C0 0 1 0 1 Channel Output Mode Per Channel Tristate Message Mode BER Test Mode Reserved
14 - 11 10 - 3
Unused MSG7 - 0
2-1
PCC1 - 0
0
CMM = 1
Connection Memory Mode = 1 If this is high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel BER mode.
Note: For proper
-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
88
Zarlink Semiconductor Inc.
ZL50022
24.3 Connection Memory High (CM_H) Bit Assignment
Data Sheet
Connection memory high provides the detailed information required for -law and A-law conversion. ICL and OCL bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between A-law and -law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed. The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections, variable delay connections and per-channel message mode.
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
V/D
3
ICL 1
2
ICL 0
1
OCL 1
0
OCL 0
Bit
Name
Description
15 - 5 4
Unused V/D
Reserved In normal functional mode, these bits MUST be set to zero. Voice/Data Control When this bit is low, the corresponding channel is for voice. When this bit is high, the corresponding channel is for data. Input Coding Law.
ICL1-0 00 01 10 11 Input Coding Law For Voice (V/D bit = 0) CCITT.ITU A-law CCITT.ITU -law A-law w/o ABI -law w/o Magnitude Inversion For Data (V/D bit = 1) No code ABI Inverted ABI All Bits Inverted
3-2
ICL1 - 0
1-0
OCL1 - 0
Output Coding Law
OCL1-0 00 01 10 11 Output Coding Law For Voice (V/D bit = 0) CCITT.ITU A-law CCITT.ITU -law A-law w/o ABI -law w/o Magnitude Inversion For Data (V/D bit = 1) No code ABI Inverted ABI All Bits Inverted
Note 1: Note 2:
For proper
-law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
Refer to G.711 standard for detail information of different laws.
Table 55 - Connection Memory High (CM_H) Bit Assignment
89
Zarlink Semiconductor Inc.
ZL50022
25.0 Applications
Data Sheet
This section contains application-specific details for clock and crystal operation and power supply decoupling.
25.1
OSCi Master Clock Requirement
The device requires a 20 MHz master clock source at the OSCi pin when operating in Master mode or in Divided Slave with OSC mode. The clock source may be either an external clock oscillator connected to the OSCi pin, or an external crystal connected between the OSCi and OSCo pins. If an external clock source is present, OSC_EN must be tied high. Note that using a crystal is only suitable for wider tolerance applications (i.e. 100 ppm). For stratum 4E applications a clock oscillator with a tolerance of 32 ppm should be used. See Application Note ZLAN-68 for a list of Oscillators and Crystals that can be used with Zarlink PLL's and Digital Switches with embedded PLL's.
25.1.1
External Crystal Oscillator
When an external crystal oscillator is used, a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 23 on page 90. XC is a buffered version of the 20 MHz input clock connected to the internal circuitry.
4K DX
OSCi 20 MHz
1
25 pF
25 pF
XC
OSCo
Figure 23 - Crystal Oscillator Circuit The accuracy of a crystal oscillator circuit depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 23 on page 90 may be used to compensate for capacitive effects. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal accuracy only affects the output clock accuracy in the freerun or the holdover mode. The crystal specification is as follows: Frequency Tolerance Oscillation Mode Resonance Mode 20 MHz As required Fundamental Parallel
90
Zarlink Semiconductor Inc.
ZL50022
Load Capacitance Maximum Series Resistance Approximate Drive Level 20 pF - 32 pF 35 1 mW
Data Sheet
25.1.2
External Clock Oscillator
When an external clock oscillator is used, numerous parameters must be considered. They include absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo output should be left open as shown in Figure 24 on page 91. XC is a buffered version of the 20 MHz input clock connected to the internal circuitry.
4K DX
OSCi
+3.3 V
+3.3 V 20 MHz OUT GND 0.1 uF
XC
OSCo No Connection
Figure 24 - Clock Oscillator Circuit For applications requiring 32 ppm clock accuracy, the following requirements should be met: Frequency Tolerance Rise and Fall Time Duty Cycle 20.000 MHz 32 ppm 10 ns 40% to 60%
91
Zarlink Semiconductor Inc.
ZL50022
26.0 DC Parameters
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 I/O Supply Voltage Core Supply Voltage Input Voltage Input Voltage (5 V-tolerant inputs) Continuous Current at Digital Outputs Package Power Dissipation Storage Temperature Symbol VDD_IO VDD_CORE VI_3V VI_5V Io PD TS - 55 Min. -0.5 -0.5 -0.5 -0.5 Max. 5.0 2.5 VDD + 0.5 7.0 15 1.5 +125 Units V V V V mA W C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 Operating Temperature Positive Supply Positive Supply Input Voltage Input Voltage on 5 V-Tolerant Inputs Sym. TOP VDD_IO VDD_CORE VI VI_5V Min. -40 3.0 1.71 0 0 Typ. 25 3.3 1.8 3.3 5.0 Max. +85 3.6 1.89 VDD_IO 5.5 Units C V V V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 Supply Current - VDD_CORE Supply Current - VDD_IO Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current Weak Pulldown Current Input Pin Capacitance Output High Voltage Sym. IDD_CORE IDD_IO VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ CO 5 2.4 0.4 5 10 -33 33 3 2.0 0.8 5 5 Min. Typ. Max. 175 75 Units mA mA V V A A A A pF V V A pF IOH = 8 mA IOL = 8 mA 0 < V < VDD 010 Output Low Voltage 11 Output High Impedance Leakage 12 Output Pin Capacitance
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
92
Zarlink Semiconductor Inc.
ZL50022
27.0 AC Parameters
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 2 CMOS Threshold Rise/Fall Threshold Voltage High Sym. VCT VHM Level 0.5 VDD_IO 0.7 VDD_IO Units V V V Conditions
3 Rise/Fall Threshold Voltage Low VLM 0.3 VDD_IO Characteristics are over recommended operating conditions unless otherwise stated.
Timing Reference Points ALL SIGNALS V HM V CT V LM
Figure 25 - Timing Parameter Measurement Voltage Levels
93
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup to DTA Low Sym tCSD tDSD tCSS tRWS tAS tCSH tRWH tAH tDS tDH tAKD Min. 15 15 0 10 5 0 0 0 8 7 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
10 Data hold after DS rising 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory
75 185 tAKH tAKZ 4 12 8
ns ns ns ns
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 17.2 on page 47) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
tCSS
tCSH
CS
tDSD
VCT
DS R/W
VCT
tRWS
tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
VCT
tDH
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 26 - Motorola Non-Multiplexed Bus Timing - Read Access
94
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling Data setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Sym. tCSD tDSD tCSS tRWS tAS tDS tCSH tRWH tAH tDH tAKD Min. 15 15 0 10 5 0 0 0 0 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
10 Data hold from DS rising 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory
CL = 50 pF, RL = 1 K (Note 1)
55 150 tAKH tAKZ 4 12 8
ns ns ns ns
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 17.2 on page 47) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
tCSS
tCSH
CS
tDSD
VCT
DS R/W
VCT
tRWS tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access
95
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time RD setup to CS falling WR setup to CS falling Address setup to CS falling RD hold after CS rising WR hold after CS rising Address hold after CS rising Data setup to RDY high Data hold after CS rising Sym. tCSD tRS tWS tAS tRH tWH tAH tDS tDH tAKD Min. 15 10 10 5 0 0 0 8 7 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory
75 185 tAKH tAKZ 4 12 8
ns ns ns ns
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 17.2 on page 47) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
CS
tRS tRH
VCT
RD
tWS tWH
VCT
WR
tAS tAH
VALID ADDRESS
VCT
A0-A13
VCT
tDH
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access
96
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time WR setup to CS falling RD setup to CS falling Address setup to CS falling Data setup to CS falling WR hold after CS rising RD hold after CS rising Address hold after CS rising Data hold after CS rising Sym. tCSD tWS tRS tAS tDS tWH tRH tAH tDH tAKD Min. 15 10 10 5 0 0 0 10 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory
55 150 tAKH tAKZ 4 12 8
ns ns ns ns
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (Section 17.2 on page 47) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
CS
tWS tWH
VCT
WR
tRS tRH
VCT
RD
tAS tAH
VALID ADDRESS
VCT
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access
97
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW 200 Min. 100 20 20 10 10 20 60 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL TCK
tTCKH
tTCKP
tTMSS TMS
tTMSH
tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST
Figure 30 - JTAG Test Port Timing Diagram AC Electrical Characteristics - OSCi 20 MHz Input Timing Characteristic 1 2 Input frequency accuracy Duty cycle Sym. Min. -32 -100 40 Typ. Max. 32 100 60 3 Units ppm ppm % ns Notes Stratum 4E Relaxed Stratum 4E 1 14
3 Input rise or fall time tIR,tIF Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
98
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 40 20 20 55 27 27 61 67 34 34 3 20 Typ. 61
Data Sheet
Max. Units Notes 115 ns ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 90 45 45 110 55 55 122 135 69 69 3 20 Typ. 122 Max. Units Notes 220 ns ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz) Characteristic 1 2 3 4 5 6 7 8 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time CKi Input Clock Cycle to Cycle Variation Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi tCVC 0 Min. 90 110 110 220 110 110 244 270 135 135 3 20 Typ. 244 Max. Units Notes 420 ns ns ns ns ns ns ns ns
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
99
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
100
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps tSIH2 tSIH4 tSIH8 tSIH16 8 8 8 8 ns ns ns ns tSIS2 tSIS4 tSIS8 tSIS16 5 5 5 5 ns ns ns ns Sym. Min. Typ. Max. Units
Data Sheet
Test Conditions
Characteristics are over recommended operating conditions unless otherwise stated.
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 31 2.048 Mbps
Bit0 Ch31
Bit7 Ch0
Bit6 Ch0
VCT
tSIS4 tSIH4
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
STi0 - 31 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 31 8.192 Mbps
Bit1 Ch127
Bit0 Ch127
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
Bit3 Ch0
Bit2 Ch0
Bit1 Ch0
Bit0 Ch0
VTT VCT
Input Frame Boundary
Figure 33 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps
101
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
FPi CKi (16.384 MHz) tSIS16 tSIH16 STi0 - 31 16.384 Mbps
Bit1 Ch255 Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0
VTT VCT
Input Frame Boundary
Figure 34 - ST-BUS Input Timing Diagram when Operated at 16 Mbps
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 31 2.048 Mbps
Bit7 Ch31
Bit0 Ch0
Bit1 Ch0
VCT
tSIS4 tSIH4
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
STi0 - 31 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 31 8.192 Mbps
Bit6 Ch127
Bit7 Ch127
Bit0 Ch0
Bit1 Ch0
Bit2 Ch0
Bit3 Ch0
Bit4 Ch0
Bit5 Ch0
Bit6 Ch0
Bit7 Ch0
VTT VCT
Input Frame Boundary
Figure 35 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps
102
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
FPi CKi (16.384 MHz) tSIS16 tSIH16 STi0 - 31 16.384 Mbps
Bit6 Ch255 Bit7 Ch255 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VTT VCT
Input Frame Boundary
Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps
103
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - ST-BUS/GCI-Bus Output Timing Characteristic 1 STio Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps tSOD2 tSOD4 tSOD8 tSOD16 tSOD2 tSOD4 tSOD8 tSOD16 tSOD2 tSOD4 tSOD8 tSOD16 1 1 1 1 0 0 0 0 -6 -6 -6 -6 8 8 8 8 6 6 6 6 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns Sym. Min. Typ. Max. Units
Data Sheet
Test Conditions CL = 30 pF Master Mode
Multiplied Slave Mode
Divided Slave Mode
Characteristics are over recommended operating conditions unless otherwise stated.
FPo0 CKo0 (4.096 MHz)
tSOD2 STio0 - 31 2.048 Mbps
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
VCT
tSOD4 STio0 - 31 4.096 Mbps
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
VCT
tSOD8 STio0 - 31 8.192 Mbps
Bit0 Ch127 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0
VCT
tSOD16 STio0 - 31 16.384 Mbps
Bit2 Bit1 Bit0 Bit7 Ch255 Ch255 Ch255 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0 Bit7 Ch1 Bit6 Ch1 Bit5 Ch1 Bit4 Ch1 Bit3 Ch1 Bit2 Ch1 Bit1 Ch1
VCT
Output Frame Boundary
Figure 37 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
104
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
FPo0 CKo0 (4.096 MHz) tSOD2 STio0 - 31 2.048 Mbps
Bit7 Ch31 Bit0 Ch0 Bit1 Ch0
VCT
tSOD4 STio0 - 31 4.096 Mbps
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
VCT
tSOD8 STio0 - 31 8.192 Mbps
Bit7 Ch127 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VCT
tSOD16 STio0 - 31 16.384 Mbps
Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0 Bit0 Ch1 Bit1 Ch1 Bit2 Ch1 Bit3 Ch1 Bit4 Ch1 Bit5 Ch1 Bit6 Ch1
VCT
Output Frame Boundary
Figure 38 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
105
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - ST-BUS/GCI-Bus Output Tristate Timing Characteristic 1 STio Delay - Active to High-Z Sym. tDZ Min. -2 -3 -8 -2 -3 -8 Typ. Max. 8 7 0 8 7 0 77 260 138 77 tDZ_ODE 77 260 138 77 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions* Master Mode Multiplied Slave Mode Divided Slave Mode Master Mode Multiplied Slave Mode Divided Slave Mode Master or Multiplied Slave Mode Divided Slave Mode
2
STio Delay - High-Z to Active
tZD
3
Output Drive Enable (ODE) Delay - High-Z to Active CKi @ 4.096MHz CKi @ 8.192MHz CKi @ 16.384MHz
tZD_ODE
4
Output Drive Enable (ODE) Delay - Active to High-Z CKi @ 4.096MHz CKi @ 8.192MHz CKi @ 16.384MHz
Master or Multiplied Slave Mode Divided Slave Mode
Characteristics are over recommended operating conditions unless otherwise stated. * Test condition is RL = 1 k, CL = 30 pF; high impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge CL.
FPo0
VCT
CKo0 tDZ STio Valid Data tZD STio Tristate
VCT
Tristate
VCT
Valid Data
VCT
Figure 39 - Serial Output and External Control
ODE tZD_ODE STio HiZ Valid Data tDZ_ODE HiZ
VCT
VCT
Figure 40 - Output Drive Enable (ODE)
106
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Slave Mode Input/Output Frame Boundary Alignment Characteristic 1 2 Input and Output Frame Offset in Divided Slave Mode Input and Output Frame Offset in Multiplied Slave Mode Sym.
tFBOS tFBOS
Data Sheet
Min. 5 2
Typ.
Max. 13 10
Units ns ns
Notes
Input reference jitter is equal to zero.
Characteristics are over recommended operating conditions unless otherwise stated.
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary tFBOS Output Frame Boundary
FPo0 CKo0 (4.096 MHz)
Figure 41 - Input and Output Frame Boundary Offset
107
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPW0 FPo0/FPo3 tFODF0 tCKP0 tCKH0 CKo0/CKo3 tfCK0 Output Frame Boundary trCK0 tCKL0 VCT tFODR0 VCT
Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram
AC Electrical Characteristics - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo0 Output Pulse Width FPo0 Output Delay from the FPo0 falling edge to the output frame boundary FPo0 Output Delay from the output frame boundary to the FPo0 rising edge CKo0 Output Clock Period CKo0 Output High Time CKo0 Output Low Time CKo0 Output Rise/Fall Time
Sym. tFPW0 tFODF0 tFODR0 tCKP0 tCKH0 tCKL0 trCK0, tfCK0
Min. 239 117 117 239 117 117
Typ. 244
Max. 249 127 127
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
244
249 127 127 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo0 Output Pulse Width FPo0 Output Delay from the FPo0 falling edge to the output frame boundary FPo0 Output Delay from the output frame boundary to the FPo0 rising edge CKo0 Output Clock Period CKo0 Output High Time CKo0 Output Low Time CKo0 Output Rise/Fall Time
Sym. tFPW0 tFODF0 tFODR0 tCKP0 tCKH0 tCKL0 trCK0, tfCK0
Min. 218 117 97 218 117 97
Typ. 244
Max. 270 127 146
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
244
270 127 146 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
108
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPW1 FPo1/FPo3 tFODF1 tCKP1 tCKH1 CKo1/CKo3 tfCK1 Output Frame Boundary trCK1 tCKL1 VCT tFODR1 VCT
Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram
AC Electrical Characteristics - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo1 Output Pulse Width FPo1 Output Delay from the FPo1 falling edge to the output frame boundary FPo1 Output Delay from the output frame boundary to the FPo1 rising edge CKo1 Output Clock Period CKo1 Output High Time CKo1 Output Low Time CKo1 Output Rise/Fall Time
Sym. tFPW1 tFODF1 tFODR1 tCKP1 tCKH1 tCKL1 trCK1, tfCK1
Min. 117 56 56 117 56 56
Typ. 122
Max. 127 66 66
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
122
127 66 66 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo1 Output Pulse Width FPo1 Output Delay from the FPo1 falling edge to the output frame boundary FPo1 Output Delay from the output frame boundary to the FPo1 rising edge CKo1 Output Clock Period CKo1 Output High Time CKo1 Output Low Time CKo1 Output Rise/Fall Time
Sym. tFPW1 tFODF1 tFODR1 tCKP1 tCKH1 tCKL1 trCK1, tfCK1
Min. 106 56 46 106 46 46
Typ. 122
Max. 127 66 66
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
122
148 87 66 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
109
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPW2 FPo2/FPo3 tFODF2 tCKP2 tCKH2 CKo2/CKo3 tfCK2 Output Frame Boundary trCK2 tCKL2 VCT tFODR2 VCT
Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram
AC Electrical Characteristics - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo2 Output Pulse Width FPo2 Output Delay from the FPo2 falling edge to the output frame boundary FPo2 Output Delay from the output frame boundary to the FPo2 rising edge CKo2 Output Clock Period CKo2 Output High Time CKo2 Output Low Time CKo2 Output Rise/Fall Time
Sym. tFPW2 tFODF2 tFODR2 tCKP2 tCKH2 tCKL2 trCK2, tfCK2
Min. 56 25 25 56 25 25
Typ. 61
Max. 66 36 36
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
61
66 36 36 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo2 Output Pulse Width FPo2 Output Delay from the FPo2 falling edge to the output frame boundary FPo2 Output Delay from the output frame boundary to the FPo2 rising edge CKo2 Output Clock Period CKo2 Output High Time CKo2 Output Low Time CKo2 Output Rise/Fall Time
Sym. tFPW2 tFODF2 tFODR2 tCKP2 tCKH2 tCKL2 trCK2, tfCK2
Min. 56 25 25 47 17 17
Typ. 61
Max. 66 36 36
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
61
76 43 43 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
110
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPW3 FPo3 tFODF3 tCKP3 tCKH3 CKo3 tfCK3 Output Frame Boundary trCK3 tCKL3 VCT tFODR3 VCT
Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram
AC Electrical Characteristics - FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or Multiplied Slave
Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic 1 2 3 4 5 6 7 FPo3 Output Pulse Width FPo3 Output Delay from the FPo3 falling edge to the output frame boundary FPo3 Output Delay from the output frame boundary to the FPo3 rising edge CKo3 Output Clock Period CKo3 Output High Time CKo3 Output Low Time CKo3 Output Rise/Fall Time
Sym. tFPW3 tFODF3 tFODR3 tCKP3 tCKH3 tCKL3 trCK3, tfCK3
Min. 27 10 12 27 12 12
Typ. 30.5
Max. 34 18 21
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
30.5
34 19 19 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPo3 and CKo3 (32.768 MHz) Timing (Multiplied Slave Mode with more than 10 ns of Cycle to
Cycle Variation on CKi
Characteristic 1 2 3 4 5 6 7 FPo3 Output Pulse Width FPo3 Output Delay from the FPo3 falling edge to the output frame boundary FPo3 Output Delay from the output frame boundary to the FPo3 rising edge CKo3 Output Clock Period CKo3 Output High Time CKo3 Output Low Time CKo3 Output Rise/Fall Time
Sym. tFPW3 tFODF3 tFODR3 tCKP3 tCKH3 tCKL3 trCK3, tfCK3
Min. 27 12 12 17 5 12
Typ. 30.5
Max. 34 19 19
Units ns ns ns ns ns ns ns
Notes
CL = 30 pF
30.5
44 29 18 5
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
111
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
FPo0
VCT
tCKP4 tCKH4 CKo4 tfCK4 Output Frame Boundary trCK4 tCKL4 VCT
Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz)
AC Electrical Characteristics - CKo4 (1.544 MHz) Timing (Only when DPLL is active) Characteristic 1 2 3 4 CKo4 Output Clock Period CKo4 Output High Time CKo4 Output Low Time CKo4 Output Rise/Fall Time Sym. tCKP4 tCKH4 tCKL4 trCK4, tfCK4 Min. 645 320 320 Typ. 648 324 324 Max. 650 327 327 5 Units ns ns ns ns
CL = 30 pF
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - CKo4 (2.048 MHz) Timing (Only when DPLL is active) Characteristic 1 2 3 4 CKo4 Output Clock Period CKo4 Output High Time CKo4 Output Low Time CKo4 Output Rise/Fall Time Sym. tCKP4 tCKH4 tCKL4 trCK4, tfCK4 Min. 485 241 241 Typ. 488 244 244 Max. 492 247 247 5 Units ns ns ns ns
CL = 30 pF
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
112
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
tFPW5 FPo5 (shares output pin with FPo_OFF2) VCT tFODF5 tCKP5 tCKH5 CKo5 tfCK5 Output Frame Boundary trCK5 tCKL5 VCT tFODR5
Figure 47 - CKo5 Timing Diagram (19.44 MHz)
AC Electrical Characteristics - CKo5 (19.44 MHz) Timing (Only when DPLL is active) Characteristic 1 2 3 4 5 6 7 FPo5 Output Pulse Width FPo5 Output Delay from the FPo5 falling edge to the output frame boundary FPo5 Output Delay from the output frame boundary to the FPo5 rising edge CKo5 Output Clock Period CKo5 Output High Time CKo5 Output Low Time CKo5 Output Rise/Fall Time Sym. tFPW5 tFODF5 tFODR5 tCKP5 tCKH5 tCKL5 trCK5, tfCK5 Min. 49 22 21 50 23 24 Typ. 51 25 25 51 25 25 Max. 55 28 32 53 27 28 5 Units ns ns ns ns ns ns ns
CL = 30 pF
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
113
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - REF0-3 Reference Input to CKo Output Timing Characteristic 1 2 3 Minimum Input Pulse Width High or Low Input Rise or Fall Time REF input to CKo0 output delay (no input jitter) REF at 8 kHz, 2.048, 4.096, 8.192, 16.384 MHz REF at 1.544 MHz REF at 19.44 MHz Sym. tRPMIN tIR, (or tIF) tRD -7 6 -10 Min. 16 5 0 15 -2 Max. Units ns ns ns ns ns
Data Sheet
Notes 1,2,3,14
Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
tRPMIN tRD REF0-3 VCT
FPo[n]
tIR
VCT
CKo[n]
VCT
Figure 48 - REF0 - 3 Reference Input/Output Timing
114
Zarlink Semiconductor Inc.
ZL50022
AC Electrical Characteristics - Master Mode Output Timing Characteristic 1 2 3 4 CKo0 to CKo1 (8.192 MHz) delay CKo0 to CKo2 (16.384 MHz) delay CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay CKo0 to CKo4 (1.544 MHz/2.048 MHz) delay CKo4 at 1.544 MHz CKo4 at 2.048 MHz CKo0 to CKo5 (19.44 MHz) delay Sym. tC1D tC2D tC3D tC4D Min. -1 -1 -4 Max. 2 3 0
Data Sheet
Units ns ns ns
Notes 1-5,14
-12 -2 6
-7 3 12
ns ns ns
5
tC5D
Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
AC Electrical Characteristics - Divided Slave Mode Output Timing Characteristic 1 2 3 CKo0 to CKo1 (8.192 MHz) delay CKo0 to CKo2 (16.384 MHz) delay CKo0 to CKo3 (16.384 MHz/8.192 MHz/4.096 MHz) delay Sym. tC1D tC2D tC3D Min. -1 -1 -2 Max. 2 3 2 Units ns ns ns Notes 1-5,14
Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
AC Electrical Characteristics - Multiplied Slave Mode Output Timing Characteristic 1 2 3 CKo0 to CKo1 (8.192 MHz) delay CKo0 to CKo2 (16.384 MHz) delay CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay Sym. tC1D tC2D tC3D Min. -1 -1 -1 Max. 2 3 3 Units ns ns ns Notes 1-5,14
Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
115
Zarlink Semiconductor Inc.
ZL50022
Data Sheet
FPo0
VCT
CKo0 (4.096 MHz) tC4D CKo4 (1.544 MHz) tC1D CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo5 (19.44 MHz) CKo3 (32.768 MHz) VCT tC2D VCT tC5D VCT tC3D VCT VCT
VCT
Figure 49 - Output Timing (ST-BUS Format)
116
Zarlink Semiconductor Inc.
ZL50022
DPLL Performance Characteristics - Accuracy & Switching Characteristics 1 2 3 4 5 6 7 8 9 10 Freerun Accuracy Initial Holdover Frequency Stability Pull-in/Hold-in Range (Stratum 4E) Reference Far Hysteresis Limit (Stratum 4E) Reference Near Hysteresis Limit (Stratum 4E) Reference Far Hysteresis Limit (Relaxed Stratum 4E) Reference Near Hysteresis Limit (Relaxed Stratum 4E) Output phase continuity for reference switch1 Normal output phase alignment speed (phase slope) Normal phase lock time2 Min -0.003 -0.03 -260 -82.5 -64.5 -248 -242 Max 0 0.03 260 82.5 64.5 248 242 31 56 75 Units ppm ppm ppm ppm ppm ppm ppm ns s/s s
Data Sheet
Conditions/ Notes 1,5,7 1,4,8 1,3,7,9 1,3,7,9,12 1,3,7,9,13 11 10 1,3,7,9,10
1. Reference switching to normal, holdover, or freerun mode 2. -32 to +32 ppm locking Characteristics are over recommended operating conditions unless otherwise stated. See "Performance Characteristics Notes" on page 118.
. DPLL Performance Characteristics - Output Jitter Generation (Unfiltered except for CKo5) Characteristics 1 2 3 4 5 Jitter at CKo0 and CKo3 (4.096 MHz) Jitter at CKo1 and CKo3 (8.192 MHz) Jitter at CKo2 and CKo3 (16.384 MHz) Jitter at CKo3 (4.096, 8.192, 16.384, or 32.768 MHz) Jitter at CKo4 (1.544 MHz or 2.048 MHz) 1.544 MHz 2.048 MHz Jitter at CKo5 (19.44 MHz) unfiltered jitter 500 Hz - 1.3 MHz jitter 65 kHz - 1.3 MHz jitter 12 kHz - 1.3 MHz jitter Typ. 810 800 710 670 1060 630 770 540 460 510 Units ps-pp ps-pp ps-pp ps-pp ps-pp ps-pp ps-pp ps-pp ps-pp ps-pp Conditions/Notes* 1-6,14
6
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * See "Performance Characteristics Notes" on page 118
117
Zarlink Semiconductor Inc.
ZL50022
Performance Characteristics Notes
Data Sheet
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. 1. Jitter on master clock input (XIN) is 100 ps pp or less. 2. Jitter on reference input (REF0-3) is 2 ns pp or less. 3. Normal Mode selected. 4. Holdover Mode selected. 5. Freerun Mode selected. 6. Jitter is measured without an output filter. 7. Accuracy of master clock input (XIN) is 0 ppm. 8. Accuracy of master clock input (XIN) is 100 ppm. 9. Capture range is +/-260 ppm; inaccuracy of XIN shifts this range. 10. Phase alignment speed (phase slope) is programmed to 7 ns/125s. 11. Any input reference switch or state switch (i.e. REF0 to REF3, Normal to Holdover, etc.). 12. Multi-period near limits and far limits are programmed to +/-64.713ppm & +/-82.487ppm respectively. (ST4_LIM = 1) 13. Multi-period near limits and far limits are programmed to +/-240ppm & +/-250ppm respectively. (ST4_LIM = 0) 14. 30 pF load on output pin.
118
Zarlink Semiconductor Inc.
b
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 214440 26June03
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of ZL5002206

	To Download ZL5002206 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .